A 0.32–128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm
Custom accelerators improve the energy efficiency, area efficiency, and performance of
deep neural network (DNN) inference. This article presents a scalable DNN accelerator …
deep neural network (DNN) inference. This article presents a scalable DNN accelerator …
Freely scalable and reconfigurable optical hardware for deep learning
As deep neural network (DNN) models grow ever-larger, they can achieve higher accuracy
and solve more complex problems. This trend has been enabled by an increase in available …
and solve more complex problems. This trend has been enabled by an increase in available …
Dimm-link: Enabling efficient inter-dimm communication for near-memory processing
DIMM-based near-memory processing architectures (DIMM-NMP) have received growing
interest from both academia and industry. They have the advantages of large memory …
interest from both academia and industry. They have the advantages of large memory …
A 0.297-pJ/bit 50.4-Gb/s/wire inverter-based short-reach simultaneous bi-directional transceiver for die-to-die interface in 5-nm CMOS
Y Nishi, JW Poulton, WJ Turner, X Chen… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
This article presents a clock-forwarded, inverter-based short-reach simultaneous bi-
directional (ISR-SBD) physical layer (PHY) targeted for die-to-die communication over …
directional (ISR-SBD) physical layer (PHY) targeted for die-to-die communication over …
GaN memory operational at 300° C
The most commonly used memory cells, namely a 32-bit-bit read-only memory, a 1-bit 4-
transistor static random-access memory, D latch, and D flip-flop (DFF), were demonstrated …
transistor static random-access memory, D latch, and D flip-flop (DFF), were demonstrated …
Silicon-interconnect fabric for fine-pitch (≤ 10 μm) heterogeneous integration
The apparent saturation of aggressive Moore's law scaling of semiconductor technologies is
pushing the boundaries of traditional packaging and integration schemes to accommodate …
pushing the boundaries of traditional packaging and integration schemes to accommodate …
PINE: photonic integrated networked energy efficient datacenters (ENLITENED program)
We review the motivation, goals, and achievements of the Photonic Integrated Networked
Energy efficient datacenter (PINE) project, which is part of the Advanced Research Projects …
Energy efficient datacenter (PINE) project, which is part of the Advanced Research Projects …
30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links
A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a
one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random …
one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random …
Chiplet cloud: Building ai supercomputers for serving large generative language models
Large language models (LLMs) such as ChatGPT have demonstrated unprecedented
capabilities in multiple AI tasks. However, hardware inefficiencies have become a significant …
capabilities in multiple AI tasks. However, hardware inefficiencies have become a significant …
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
Y Nishi, JW Poulton, WJ Turner, X Chen… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
This article presents an inverter-based short-reach ac-coupled toggle (ISR-ACT) link
targeted for short-reach die-to-die communication over silicon interposer or similar high …
targeted for short-reach die-to-die communication over silicon interposer or similar high …