Multiplier Design using Machine Learning Alogorithms for Energy Efficiency

J Juma, RM Mdodo, D Gichoya - Journal of VLSI circuits and …, 2023 - vlsijournal.com
Multiplier Design using Machine Learning Alogorithms for Energy Efficiency Page 1 Journal
of VLSI circuits and systems, , ISSN 2582-1458 28 RESEARCH ARTICLE WWW.VLSIJOURNAL.COM …

Machine learning based novel architecture implementation for image processing mechanism

J Jonnerby, A Brezger, H Wang - International Journal of communication …, 2023 - ijccts.org
When an image captured in low-light, it gets the low visibility. To overcome the low visibility
of the image, some operations are to be performed. But in this paper image enhancement is …

Design and performance analysis of low power and energy-efficient vedic multipliers

S Shaik, S Kanapala, V Vijay, CS Pittala - International Journal of System …, 2023 - Springer
This paper explores low-power and energy-efficient multi-bit Vedic Multiplier (VM)
architectures at a supply voltage as low as 0.6 V. Energy efficient architectures are a …

Machine Learning Dependent Arithmetic Module Realization for High-Speed Computing

C Marangunic, F Cid, A Rivera… - Journal of VLSI circuits and …, 2022 - vlsijournal.com
Since last few years, the tiny size of MOSFET, that is less than tens of nanometers, created
some operational problems such as increased gate-oxide leakage, amplified junction …

Fundamental Flip-Flop Design: Comparative Analysis

KJ Bosco, SM Pavalam, LJ Mpamije - Journal of VLSI circuits and …, 2023 - vlsijournal.com
A latch is used to store single bit information. It is a level triggered device. These are the
building blocks for sequential circuits. The basic working of D-Latch is that input data will be …

Faster billing mechanism for super market purchases

F BEYENE, K NEGASH, G SEMEON - International Journal of …, 2023 - ijccts.org
This research paper proposes the Internet of Things (IOT) is relying on exchange of
information and work progress through radio frequency identification, which is an emerging …

Memory Module: High-Speed Low Latency Data Storing Modules

D Klein, S Dech, B Raddwine, E Uken - Journal of VLSI circuits and …, 2023 - vlsijournal.com
The electronics devices are facing a foremost drawback of standby leakage, which severely
impacting the electronics industry from the past few decades. As well as the need for cache …

Fundamental Data Seperator using Threshold Logic at Low-Supply Voltages

Q Hugh, F Soria, CC Kingdon… - Journal of VLSI circuits …, 2022 - vlsijournal.com
In digital terminology, a device that compares two numbers which are represented in binary
format and determines whether one of the two inputs are lesser than or equal to or greater …

ADC: Novel Methodology for Code Converter Application for Data Processing

HM Snousi, FA Aleej, MF Bara… - Journal of VLSI circuits …, 2022 - vlsijournal.com
Abstract An innovative “Multiplexer based Thermometer to Binary code encoder” is
presented in this paper. This paper shows a relative decrease in the total count of …

LowPhy module improvization using novel methodology for 5G Technology

MR USIKALU, ENC OKAFOR - International Journal of communication and …, 2023 - ijccts.org
In a communication system, OFDM is the best technique for high speed transfer amplification
in a communication network. The principal downside in the OFDM system was PAPR (Peak …