A survey of CPU-GPU heterogeneous computing techniques
As both CPUs and GPUs become employed in a wide range of applications, it has been
acknowledged that both of these Processing Units (PUs) have their unique features and …
acknowledged that both of these Processing Units (PUs) have their unique features and …
An overview of nonvolatile emerging memories—Spintronics for working memories
T Endoh, H Koike, S Ikeda, T Hanyu… - IEEE journal on …, 2016 - ieeexplore.ieee.org
This paper reviews emerging nonvolatile random access memories (RAM) in recent years. It
first benchmarks ferroelectric RAM (FeRAM), phase change RAM (PCRAM), resistive RAM …
first benchmarks ferroelectric RAM (FeRAM), phase change RAM (PCRAM), resistive RAM …
Destiny: A tool for modeling emerging 3d nvm and edram caches
The continuous drive for performance has pushed the researchers to explore novel memory
technologies (eg nonvolatile memory) and novel fabrication approaches (eg 3D stacking) in …
technologies (eg nonvolatile memory) and novel fabrication approaches (eg 3D stacking) in …
Doppelgänger: A cache for approximate computing
Modern processors contain large last level caches (LLCs) that consume substantial energy
and area yet are imperative for high performance. Cache designs have improved …
and area yet are imperative for high performance. Cache designs have improved …
A survey of techniques for modeling and improving reliability of computing systems
Recent trends of aggressive technology scaling have greatly exacerbated the occurrences
and impact of faults in computing systems. This has madereliability'a first-order design …
and impact of faults in computing systems. This has madereliability'a first-order design …
DESTINY: A comprehensive tool with 3D and multi-level cell memory modeling capability
To enable the design of large capacity memory structures, novel memory technologies such
as non-volatile memory (NVM) and novel fabrication approaches, eg, 3D stacking and multi …
as non-volatile memory (NVM) and novel fabrication approaches, eg, 3D stacking and multi …
A 340 mV-to-0.9 V 20.2 Tb/s source-synchronous hybrid packet/circuit-switched 16× 16 network-on-chip in 22 nm tri-gate CMOS
G Chen, MA Anders, H Kaul… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
A 16× 16 mesh network-on-chip (NoC) is fabricated in 22 nm tri-gate CMOS for high-
throughput, energy-efficient on-chip interconnect in multi-core processors and systems-on …
throughput, energy-efficient on-chip interconnect in multi-core processors and systems-on …
Exploring and analyzing the real impact of modern on-package memory on HPC scientific kernels
High-bandwidth On-Package Memory (OPM) innovates the conventional memory hierarchy
by augmenting a new on-package layer between classic on-chip cache and off-chip DRAM …
by augmenting a new on-package layer between classic on-chip cache and off-chip DRAM …
Architectural advancement of digital low-dropout regulators
Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-
grained power delivery and management in system-on-chips (SoCs) due to their process …
grained power delivery and management in system-on-chips (SoCs) due to their process …
Compact and supply-voltage-scalable temperature sensors for dense on-chip thermal monitoring
This paper presents compact and voltage-scalable temperature sensor circuits for
implementing dynamic thermal management (DTM) in high-performance microprocessors …
implementing dynamic thermal management (DTM) in high-performance microprocessors …