Energy-efficient computation is critical if we are going to continue to scale performance in
power-limited systems. For floating-point applications that have large amounts of data …

Two new floating-point fused multiply-add architectures for the single instruction execution of
(A times B)+ C are presented. The three-path architecture uses parallel hardware paths …

In this paper, an efficient multiple-precision floating-point fused multiply-add (FMA) unit is
proposed. The proposed FMA supports not only single-precision, double-precision, and …

A microprocessor is configured for unchained and chained modes of split execution of a
fused compound arithmetic operation. In both modes of split execution, a first execution unit …

Automatic video editing is receiving increasingly attention as the digital camera technology
develops further and social media sites such as YouTube and Flickr become popular …

This paper presents a novel design for a fused floating-point four-term dot product unit. The
dot product is one of the most frequently used operations for a wide variety of graphics …

Abstract Multiply-Add Fused (MAF) units play a key role in the processor׳ s performance for a
variety of applications. The objective of this paper is to present a multi-functional, multiple …

This brief presents a dedicated unit for the combined operation of floating-point (FP) division
followed by addition/subtraction-the divide-add fused (DAF). The goal of this unit is to …

A new floating-point fused multiply-add (FMA) design for the execution of (A times B)+ C as a
single instruction is presented. The bridge fused multiply-add unit is a design intended to …

The design of a component to perform parallel addition of multiple floating-point (FP)
operands is explored in this work. In particular, a 3-input FP adder is discussed in more …