Method for finding global extrema of a set of shorts distributed across an array of parallel processing elements

M Beaumont - US Patent 7,574,466, 2009 - Google Patents
(57) ABSTRACT A method for finding an extrema for an n-dimensional array having a
plurality of processing elements, the method includes determining within each processing …

Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements

M Beaumont - US Patent 7,447,720, 2008 - Google Patents
US7447720B2 - Method for finding global extrema of a set of bytes distributed across an array
of parallel processing elements - Google Patents US7447720B2 - Method for finding global …

Method for finding local extrema of a set of values for a parallel processing element

M Beaumont - US Patent 7,454,451, 2008 - Google Patents
Select an address for a next odd-/72 numbered byte from register file even set of values,
determining a first extrema from the odd set of values, determining a second extrema from …

Parallel processing computer systems with reduced power consumption and methods for providing the same

AC Felch, RH Granger - US Patent 8,200,992, 2012 - Google Patents
This invention provides a computer system architecture and method for providing the same
which can include a web page search node including a web page collection. The system …

Reconfigurable processing system and method

JR Nickolls, SD Johnson, M Williams, E Mirsky… - US Patent …, 2005 - Google Patents
Conventional processing Systems utilize parallel process ing in an inefficient manner.
Example conventional proces sors include scalar, Very Long Instruction Word (VLIW) …

Apparatus and method for matrix data processing

GN Nair, GG Nair - US Patent 6,944,747, 2005 - Google Patents
2. Background Art Signal processing may be described as the mathematical manipulation of
Signals in a predetermined manner to enhance, modify or otherwise alter the Signal …

Reconfigurable array processor for floating-point operations

HM Yang, MH Jo, IH Park, KY Choi - US Patent 8,078,835, 2011 - Google Patents
A processor for performing floating-point operations includes an array of processing
elements arranged to enable a floating-point operation. Each processing element includes …

Method and apparatus for managing transaction requests in a multi-node architecture

M Khare, A Kumar, I Schoinas, LP Looi - US Patent 6,971,098, 2005 - Google Patents
Embodiments of the present invention relate to methods and apparatus for managing
transaction requests in a multi-node architecture. In one embodiment, a previously received …

Architecture and execution for efficient mixed precision computations in single instruction multiple data/thread (SIMD/T) devices

M Lukyanov, A Grosul, M Alsup, B Beylin - US Patent 10,061,592, 2018 - Google Patents
A method for improving power, performance, area (PPA) for mixed precision computations in
a processing environment. The method includes determining a braiding factor as a number …

Physics processing unit instruction set architecture

M Maher, J Bordes, D Sequeira… - US Patent App. 10 …, 2005 - Google Patents
An efficient quasi-custom instruction set for Physics Processing Unit (PPU) is enabled by
balancing the dictates of a parallel arrangement of multiple, independent vector processors …