Non-volatile 2D MoS2/black phosphorus heterojunction photodiodes in the near- to mid-infrared region

Y Zhu, Y Wang, X Pang, Y Jiang, X Liu, Q Li… - Nature …, 2024 - nature.com
Cutting-edge mid-wavelength infrared (MWIR) sensing technologies leverage infrared
photodetectors, memory units, and computing units to enhance machine vision. Real-time …

11-bit column-parallel single-slope ADC with first-step half-reference ramping scheme for high-speed CMOS image sensors

HJ Kim - IEEE Journal of Solid-State Circuits, 2021 - ieeexplore.ieee.org
A first-step half-reference ramping (FHR) readout scheme is presented in this study for high
frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the …

2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

G Wang, Q Chen, J Xu, K Nie - Microelectronics Journal, 2023 - Elsevier
To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for
high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout …

A 12-bit two-step single-slope ADC with a constant input-common-mode level resistor ramp generator

Q Zhang, N Ning, Z Zhang, J Li, K Wu… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This article presents a 12-bit column-parallel two-step single-slope analog-to-digital
converter (SS ADC). With the merging of analog memory capacitor and input sampling …

A high area-efficiency 14-bit SAR ADC with hybrid capacitor DAC for array sensors

Q Zhang, N Ning, J Li, Q Yu, Z Zhang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This paper proposes a high area-efficiency 14-bit column-parallel successive approximation
register (SAR) analog-to-digital converter (ADC) for array sensors. A novel hybrid capacitor …

An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative …

H Pahlavanzadeh, MA Karami - AEU-International Journal of Electronics …, 2022 - Elsevier
A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme
suitable for single-ended successive approximation register (SAR) analog-to-digital …

A 12-bit column-parallel two-step single-slope ADC with a foreground calibration for CMOS image sensors

Q Zhang, N Ning, J Li, Q Yu, K Wu, Z Zhang - IEEE Access, 2020 - ieeexplore.ieee.org
This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-to-
digital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output …

A 12-bit single slope ADC with multi-step structure and ramp calibration technique for image sensors

H Li, D Liu, Y Liang, A Hu, Z Nie, C Zhang, K Li… - Microelectronics …, 2023 - Elsevier
This paper presents a novel multi-step single slope analog to digital converter (MS SS ADC).
The proposed ADC splits the 12-bit conversion into 3 steps, including 1-bit half section …

CMOS image sensor with two-step single-slope ADC using differential ramp generator

SY Park, HJ Kim - IEEE Transactions on Electron Devices, 2021 - ieeexplore.ieee.org
This study presents a CMOS image sensor (CIS) with a two-step single-slope (TS-SS)
analog-to-digital convertor (ADC), wherein the differential topology characteristics of a ramp …

Fully integrated analog machine learning classifier using custom activation function for low resolution image classification

ST Chandrasekaran, A Jayaraj… - … on Circuits and …, 2021 - ieeexplore.ieee.org
This paper presents fully-integrated analog neural network classifier architecture for low
resolution image classification that eliminates memory access. We design custom activation …