Edge computing-based SAT-video coding for remote sensing

TA Bui, PJ Lee, KY Chen, CR Chen, CSJ Liu… - IEEE …, 2022 - ieeexplore.ieee.org
This paper proposes an edge computing-based video coding implementation on an Earth
observation satellite (SAT-video coding), which can encode video using limited resources …

Complexity scalability for real-time HEVC encoders

G Correa, P Assuncao, L Agostini… - Journal of Real-Time …, 2016 - Springer
The high efficiency video coding (HEVC) standard achieves improved compression
efficiency in comparison to previous standards at the cost of much higher computational …

Модель размещения данных во внутренней памяти вычислителя, реализующего схему кодирования данных в режиме сцепления блоков

МО Таныгин, ААА Ахмад… - Известия Юго-Западного …, 2024 - science.swsu.ru
Аннотация Цель исследования. В статье исследуются особенности синтеза
специализированных устройств, выполняющих контроль целостности и аутентичности …

Real-time motion estimation diamond search algorithm for the new high efficiency video coding on FPGA

R Khemiri, H Kibeya, H Loukil, FE Sayadi, M Atri… - … Integrated Circuits and …, 2018 - Springer
High efficiency video coding (HEVC) is the latest video coding standard aimed to replace the
H. 264/AVC standard according to its high coding performance, which allows it to be mostly …

Cogeneration of fast motion estimation processors and algorithms for advanced video coding

JL Nunez-Yanez, A Nabina, E Hung… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
This paper presents a flexible and scalable motion estimation processor capable of
supporting the processing requirements for high-definition (HD) video using the H. 264 …

MESIP: A configurable and data reusable motion estimation specific instruction-set processor

SD Kim, MH Sunwoo - … transactions on circuits and systems for …, 2013 - ieeexplore.ieee.org
This paper proposes a new motion estimation (ME)-specific instruction-set processor
(MESIP) with a novel search scan order with high data reusability, to efficiently implement …

Multi-standard reconfigurable motion estimation processor for hybrid video codecs

JL Nunez-Yanez, T Spiteri, G Vafiadis - IET Computers & Digital Techniques, 2011 - IET
This study presents a programmable and configurable motion estimation (ME) processor
capable of performing ME across several state-of-the-art video codecs that include multiple …

A high performance hardware architecture for multi-frame hierarchical motion estimation

H Ho, R Klepko, N Ninh, D Wang - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
This paper presents the architecture design and FPGA implementation of a multi-frame
hierarchical motion estimation (MFHME) circuit. The target application of the circuit is high …

A high throughput two-dimensional discrete cosine transform and MPEG4 motion estimation using vector coprocessor

S Agha, UA Gulzari, F Shaheen, F Jan - Journal of Real-Time Image …, 2020 - Springer
In this work a configurable and scalable vector coprocessor for real time processing of
MPEG4 motion estimation (ME) and two-dimensional DCT (2D DCT) is presented. A …

Сегментация древовидных структур данных и их параллельная обработка в методах аутентификации, основанных на кодировании в режиме сцепления …

МО Таныгин, АА Чеснокова - Известия Юго-Западного …, 2024 - science.swsu.ru
Аннотация Цель исследования. В задачах аутентификации групп сообщений,
кодированных в режиме сцепления блоков, возникает необходимость формирования и …