A review of in-memory computing architectures for machine learning applications

S Bavikadi, PR Sutradhar, KN Khasawneh… - Proceedings of the …, 2020 - dl.acm.org
to meet the extensive computational load presented by the rapidly growing Machine
Learning (ML) and Artificial Intelligence (AI) algorithms such as Deep Neural Networks …

Custom hardware architectures for deep learning on portable devices: a review

KS Zaman, MBI Reaz, SHM Ali… - … on Neural Networks …, 2021 - ieeexplore.ieee.org
The staggering innovations and emergence of numerous deep learning (DL) applications
have forced researchers to reconsider hardware architecture to accommodate fast and …

A survey on machine learning accelerators and evolutionary hardware platforms

S Bavikadi, A Dhavlle, A Ganguly… - IEEE Design & …, 2022 - ieeexplore.ieee.org
Advanced computing systems have long been enablers for breakthroughs in artificial
intelligence (AI) and machine learning (ML) algorithms, either through sheer computational …

STT-BNN: A novel STT-MRAM in-memory computing macro for binary neural networks

TN Pham, QK Trinh, IJ Chang… - IEEE Journal on …, 2022 - ieeexplore.ieee.org
This paper presents a novel architecture for in-memory computation of binary neural network
(BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are …

Memristive dynamics enabled neuromorphic computing systems

B Yan, Y Yang, R Huang - Science China Information Sciences, 2023 - Springer
The slowing down of transistor scaling and explosive growth for intelligence computing
power emerge as the two driving factors for the study of novel devices and materials to …

RACER: Bit-pipelined processing using resistive memory

MSQ Truong, E Chen, D Su, L Shen, A Glass… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
To combat the high energy costs of moving data between main memory and the CPU, recent
works have proposed to perform processing-using-memory (PUM), a type of processing-in …

Reconfigurable bit-serial operation using toggle SOT-MRAM for high-performance computing in memory architecture

J Wang, Y Bai, H Wang, Z Hao, G Wang… - … on Circuits and …, 2022 - ieeexplore.ieee.org
Computing in memory (CIM) is a promising candidate for high throughput and energy-
efficient data-driven applications, which mitigates the well-known memory bottleneck in Von …

Architecture of computing system based on chiplet

G Shan, Y Zheng, C Xing, D Chen, G Li, Y Yang - Micromachines, 2022 - mdpi.com
Computing systems are widely used in medical diagnosis, climate prediction, autonomous
vehicles, etc. As the key part of electronics, the performance of computing systems is crucial …

A maximally row-parallel MRAM in-memory-computing macro addressing readout circuit sensitivity and area

P Deaville, B Zhang, LY Chen… - ESSCIRC 2021-IEEE …, 2021 - ieeexplore.ieee.org
This paper presents the first MRAM-based In-Memory-Computing (IMC) macro, implemented
as a 128-kb array in an advanced-node 22nm FD-SOI technology. The design maximizes …

Look-up-table based processing-in-memory architecture with programmable precision-scaling for deep learning applications

PR Sutradhar, S Bavikadi, M Connolly… - … on Parallel and …, 2021 - ieeexplore.ieee.org
Processing in memory (PIM) architecture, with its ability to perform ultra-low-latency parallel
processing, is regarded as a more suitable alternative to von Neumann computing …