[图书][B] Memory systems: cache, DRAM, disk

B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …

Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management

J Meza, J Chang, HB Yoon, O Mutlu… - IEEE Computer …, 2012 - ieeexplore.ieee.org
Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories
such as phase-change memory (PCM) can provide much larger storage capacity than …

Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture

A Olgun, FN Bostanci… - ACM Transactions on …, 2024 - dl.acm.org
Modern computing systems access data in main memory at coarse granularity (eg, at 512-bit
cache block granularity). Coarse-grained access leads to wasted energy because the …

Bi-modal dram cache: Improving hit rate, hit latency and bandwidth

N Gulur, M Mehendale, R Manikantan… - 2014 47th Annual …, 2014 - ieeexplore.ieee.org
In this paper, we present Bi-Modal Cache-a flexible stacked DRAM cache organization
which simultaneously achieves several objectives:(i) improved cache hit ratio,(ii) moving the …

Sectored DRAM: An energy-efficient high-throughput and practical fine-grained DRAM architecture

A Olgun, F Bostanci, GF Oliveira, YC Tuğrul… - …, 2022 - research-collection.ethz.ch
There are two major sources of inefficiency in computing systems that use modern DRAM
devices as main memory. First, due to coarse-grained data transfers (size of a cache block …

Moguls: a model to explore the memory hierarchy for bandwidth improvements

G Sun, CJ Hughes, C Kim, J Zhao, C Xu, Y Xie… - Acm Sigarch Computer …, 2011 - dl.acm.org
In recent years, the increasing number of processor cores and limited increases in main
memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth …

Reducing memory access bandwidth based on prediction of memory request size

BHA Dwiel, HW Cain III, S Priyadarshi - US Patent 10,169,240, 2019 - Google Patents
US10169240B2 - Reducing memory access bandwidth based on prediction of memory
request size - Google Patents US10169240B2 - Reducing memory access bandwidth …

Tag-split cache for efficient GPGPU cache utilization

L Li, AB Hayes, SL Song, EZ Zhang - Proceedings of the 2016 …, 2016 - dl.acm.org
Modern GPUs employ cache to improve memory system efficiency. However, large amount
of cache space is underutilized due to irregular memory accesses and poor spatial locality …

COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories

S Swami, K Mohanram - Design, Automation & Test in Europe …, 2017 - ieeexplore.ieee.org
Security vulnerabilities arising from data persistence in emerging non-volatile memories
(NVMs) necessitate memory encryption to ensure data security. Whereas counter mode …

Increasing the cache efficiency by eliminating noise

P Pujara, A Aggarwal - The Twelfth International Symposium on …, 2006 - ieeexplore.ieee.org
Caches are very inefficiently utilized because not all the excess data fetched into the cache,
to exploit spatial locality, is utilized. We define cache utilization as the percentage of data …