I D'arrigo, G Falessi, MC Smayling - US Patent 5,504,706, 1996 - Google Patents
A memory array (10) is provided with a plurality of Flash EEPROM memory cells (24) that are fabricated with a single level poly process. Each of the transistor cells (24) is fabricated from …
TD Yiu, F Shone - US Patent 6,031,771, 2000 - Google Patents
A read-only memory device is provided which comprises an array of read-only memory cells arranged in rows and columns. An additional row or column of flat, single polysilicon floating …
R Strenz, W Langheinrich, M Roehrich… - US Patent …, 2015 - Google Patents
In an embodiment of the invention, a memory cell arrange ment includes a Substrate and at least one memory cell includ ing a charge storing memory cell structure and a select struc …
YC See, LE Terry, CA Cavins - US Patent 5,674,762, 1997 - Google Patents
A method of fabricating an integrated circuit (272) having memory, logic, high voltage, and high current functionality uses a modular implant process step (104) to form a drain …
K Ishibashi, S Shukuri, K Yanagisawa… - US Patent …, 2005 - Google Patents
To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a …
U Sharma, SW Sun, JR Yeargain - US Patent 6,017,792, 2000 - Google Patents
State of the art nonvolatile memory devices are typically constructed by fabricating a field effect transistor (FET) in a silicon substrate. The field effect transistor is capable of Storing …
T Maeda, H Gojohbori - US Patent 5,576,572, 1996 - Google Patents
(57) ABSTRACT Related US Application Data A semiconductor integrated circuit device having a bipolar 63 continuation of ser, No. 45,125 Apr 12, 1993, abandoned transistor and …
NC Yang, CJ Chen, CJ Lin - US Patent 5,889,711, 1999 - Google Patents
4,047,163 9/1977 Choate et al....... 340/173 R Single polysilicon mask ROM processes. Redundancy cells 4,250,570 2/1981 Tsang et al...... 265/200 are based upon a diffusion …