A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth
S Yan, E Sánchez-Sinencio - IEEE Journal of Solid-State …, 2004 - ieeexplore.ieee.org
This paper presents the design and experimental results of a continuous-time/spl Sigma//spl
Delta/modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping …
Delta/modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping …
A self-trimming 14-b 100-MS/s CMOS DAC
AR Bugeja, BS Song - IEEE Journal of Solid-State Circuits, 2000 - ieeexplore.ieee.org
A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and
dynamic linearity is presented. The DAC is based on a central core of 15 thermometer …
dynamic linearity is presented. The DAC is based on a central core of 15 thermometer …
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT Modulator Dissipating 13.7-mW
R Zanbaghi, PK Hanumolu… - IEEE Journal of Solid-State …, 2012 - ieeexplore.ieee.org
A novel low power compact loop filter using a single amplifier biquad (SAB) network is
presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique …
presented for continuous-time (CT) delta-sigma (ΔΣ) modulators. This new technique …
A 14 bit continuous-time delta-sigma A/D modulator with 2.5 MHz signal bandwidth
Z Li, TS Fiez - IEEE Journal of solid-state circuits, 2007 - ieeexplore.ieee.org
A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 mum
CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop …
CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop …
Adaptive Blocker Rejection Continuous-Time ADC for Mobile WiMAX Applications
H Kim, J Lee, T Copani, S Bazarjani… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta)
analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures …
analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures …
A 75-MHz continuous-time sigma–delta modulator employing a broadband low-power highly efficient common-gate summing stage
C Briseno-Vidrios, A Edward, A Shafik… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A wide-bandwidth (BW) power-efficient continuous-time ΣΔ modulator (CTΣΔM) is
presented. The modulator introduces a third-order filter implemented with a lossless …
presented. The modulator introduces a third-order filter implemented with a lossless …
A 20-MHz bandwidth continuous-time sigma-delta modulator with jitter immunity improved full clock period SCR (FSCR) DAC and high-speed DWA
JG Jo, J Noh, C Yoo - IEEE Journal of Solid-State Circuits, 2011 - ieeexplore.ieee.org
A 20-MHz bandwidth continuous-time (CT) sigma-delta modulator (SDM) with third-order
active-RC loop filter and 4-bit quantizer is implemented in a 0.13-μm CMOS process. The …
active-RC loop filter and 4-bit quantizer is implemented in a 0.13-μm CMOS process. The …
[图书][B] High-performance D/A-converters: Application to digital transceivers
M Clara - 2012 - books.google.com
This book deals with modeling and implementation of high performance, current-steering
D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the …
D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the …
A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering
DB Barkin, ACY Lin, DK Su… - IEEE Journal of Solid …, 2004 - ieeexplore.ieee.org
An oversampling bandpass digital-to-analog converter has been designed so as to
eliminate the carrier leak and in-band SNR degradation that accompany I and Q channel …
eliminate the carrier leak and in-band SNR degradation that accompany I and Q channel …
Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS
D Giotta, P Pessl, M Clara, W Klatzer… - Proceedings of the …, 2004 - ieeexplore.ieee.org
This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC),
oversampled and 2/sup nd/order noiseshaped. It is implemented in a 0.13/spl mu/m …
oversampled and 2/sup nd/order noiseshaped. It is implemented in a 0.13/spl mu/m …