A wide range of fault tolerance methods for FPGAs have been proposed. Approaches range
from simple architectural redundancy to fully on-line adaptive implementations. The …

In this paper we present an on-line, multi-level fault tolerant (FT) technique for system
functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our …

The abundance of configurable logic elements and routing resources in recent Field-
Programmable Gate Arrays (FPGAs) provides a cost-effective method for tolerating …

We present an integrated approach to on-line FPGA testing, diagnosis and fault tolerance, to
be used in high-reliability and high-availability hardware. The testing and diagnostic process …

In recent years the application space of reconfigurable devices has grown to include many
platforms with a strong need for fault tolerance. While these systems frequently contain …

Incremental modification and optimization in VLSI Computer-Aided Design (CAD) is of
fundamental importance. However, it has not been investigated as a discipline. Previous …

As integrated circuits encapsulate more functionality and complexity, verifying that these
devices operate correctly under all scenarios is an increasingly difficult task. Rather than …

In this paper we survey major problems faced by EDA tools in tackling deep submicron
(DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay …

Comprehensive study of incremental algorithms and solutions in the context of CAD tool
development is an open area of research with a great deal of potential. Incremental …

Methods of programming an integrated circuit (IC) such as a programmable logic device to
avoid localized defects present in the IC, and ICs capable of performing these methods. As …