Automatic generation of high-coverage tests for RTL designs using software techniques and tools

Y Zhang, W Feng, M Huang - 2016 IEEE 11th Conference on …, 2016 - ieeexplore.ieee.org
Register Transfer Level (RTL) design validation is a crucial stage in the hardware design
process. We present a new approach to enhancing RTL design validation using available …

Pre-Silicon Verification and Post-Silicon Validation Methodologies

KS Mohamed - Heterogeneous SoC Design and Verification: HW/SW …, 2024 - Springer
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Regression testing of virtual prototypes using symbolic execution

B Lin, D Qian - arXiv preprint arXiv:1601.05850, 2016 - arxiv.org
Recently virtual platforms and virtual prototyping techniques have been widely applied for
accelerating software development in electronics companies. It has been proved that these …

Post-silicon functional validation with virtual prototypes

K Cong - 2015 - search.proquest.com
Post-silicon validation has become a critical stage in the system-on-chip (SoC) development
cycle, driven by increasing design complexity, higher level of integration and decreasing …

Construction of coverage data for post-silicon validation using big data techniques

E El Mandouh, A Gamal, A Khaled… - 2017 24th IEEE …, 2017 - ieeexplore.ieee.org
Full-system FPGA prototyping is now being widely used in the industry for System-on-Chip
(SoC) verification. Prototyping platforms run tests in a fraction of time compared to traditional …

[PDF][PDF] Asurvey of virtual prototyping techniques for system development and validation

S Mu, G Pan, Z Tian, J Feng - International Journal of Computer …, 2015 - academia.edu
Recently, different kinds of computer systems like smart phones, embedded systems and
cloud servers, are more and more widely used and the system development and validation …

Coverage Evaluation and Analysis of Post-Silicon Tests with Virtual Prototypes

K Cong, F Xie - Post-Silicon Validation and Debug, 2018 - Springer
High-quality tests for post-silicon validation should be ready before a silicon device
becomes available in order to save time spent on preparing, debugging, and fixing tests …

Coverage Evaluation and Analysis of Post-Silicon Tests with Virtual

K Cong, F Xie - Post-Silicon Validation and Debug, 2018 - books.google.com
New computer systems, smartphones, wearable devices, tablets, laptops, servers, etc., are
entering the marketplace at an ever-accelerating pace. This brings enormous pressures on …

OpenRISC System-on-Chip Design Emulation

K Cong, L Lei, Z Yang, F Xie - arXiv preprint arXiv:1602.03095, 2016 - arxiv.org
Recently the hardware emulation technique has emerged as a promising approach to
accelerating hardware verification/debugging process. To fully evaluate the powerfulness of …

[PDF][PDF] A Practical Approach to Creation and Analysis of FSM Designs

P Han, W Shen - International Journal of …, 2016 - pfigshare-u-files.s3.amazonaws.com
It is a common task for register-transfer level (RTL) design developers to design a finite-state
machine (FSM). To design a complete and correct FSM design, it requires a lot of …