Building programmable resistive devices in contact holes at the crossover of a plurality of
conductor lines in more than two vertical layers is disclosed. There are plurality of first …

Semiconductor memory having both volatile and non-vola tile modes and methods of
operation. A semiconductor storage device includes a plurality of memory cells each having …

Semiconductor memory having both volatile and non-vola tile modes and methods of
operation. A semiconductor storage device includes a plurality of memory cells each having …

Semiconductor memory having both volatile and non-vola tile modes and methods of
operation. A semiconductor storage device includes a plurality of memory cells each having …

FET technologies can be used as program selectors or One Time Programmable (OTP)
element in a programmable resis tive device. Such as interconnect fuse, contact/via fuse …

Semiconductor memory having both volatile and non-volatile modes and methods of
operation. A semiconductor storage device includes a plurality of memory cells each having …

Multi-port semiconductor memory cells including a common floating body region configured
to be charged to a level indicative of a memory state of the memory cell. The multi port …

A method and system for multiple-bit programmable resistive cells having a multiple-bit
programmable resistive element and using diode as program selector are disclosed. The …

US8203873B2 - Rectifying element for a crosspoint based memory array architecture - Google
Patents US8203873B2 - Rectifying element for a crosspoint based memory array architecture …

In-system repairing or configuring faulty memories after being used in a system. In one
embodiment, a memory chip can include at least one OTP memory to store defective …