Efficient hardware architectures for accelerating deep neural networks: Survey
In the modern-day era of technology, a paradigm shift has been witnessed in the areas
involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep …
involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep …
A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications
As general-purpose processors have hit the power wall and chip fabrication cost escalates
alarmingly, coarse-grained reconfigurable architectures (CGRAs) are attracting increasing …
alarmingly, coarse-grained reconfigurable architectures (CGRAs) are attracting increasing …
Simba: Scaling deep-learning inference with multi-chip-module-based architecture
Package-level integration using multi-chip-modules (MCMs) is a promising approach for
building large-scale systems. Compared to a large monolithic die, an MCM combines many …
building large-scale systems. Compared to a large monolithic die, an MCM combines many …
In-datacenter performance analysis of a tensor processing unit
Many architects believe that major improvements in cost-energy-performance must now
come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor …
come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor …
A configurable cloud-scale DNN processor for real-time AI
J Fowers, K Ovtcharov, M Papamichael… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
Interactive AI-powered services require low-latency evaluation of deep neural network
(DNN) models-aka"" real-time AI"". The growing demand for computationally expensive …
(DNN) models-aka"" real-time AI"". The growing demand for computationally expensive …
Domain-specific hardware accelerators
Domain-specific hardware accelerators Page 1 48 COMMUNICATIONS OF THE ACM | JULY
2020 | VOL. 63 | NO. 7 contributed articles FROM THE SIMPLE embedded processor in your …
2020 | VOL. 63 | NO. 7 contributed articles FROM THE SIMPLE embedded processor in your …
ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars
A Shafiee, A Nag, N Muralimanohar… - ACM SIGARCH …, 2016 - dl.acm.org
A number of recent efforts have attempted to design accelerators for popular machine
learning algorithms, such as those involving convolutional and deep neural networks (CNNs …
learning algorithms, such as those involving convolutional and deep neural networks (CNNs …
Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks
Deep convolutional neural networks (CNNs) are widely used in modern AI systems for their
superior accuracy but at the cost of high computational complexity. The complexity comes …
superior accuracy but at the cost of high computational complexity. The complexity comes …
Maeri: Enabling flexible dataflow mapping over dnn accelerators via reconfigurable interconnects
Deep neural networks (DNN) have demonstrated highly promising results across computer
vision and speech recognition, and are becoming foundational for ubiquitous AI. The …
vision and speech recognition, and are becoming foundational for ubiquitous AI. The …
Fused-layer CNN accelerators
Deep convolutional neural networks (CNNs) are rapidly becoming the dominant approach to
computer vision and a major component of many other pervasive machine learning tasks …
computer vision and a major component of many other pervasive machine learning tasks …