Symbolic execution based test-patterns generation algorithm for hardware Trojan detection
L Shen, D Mu, G Cao, M Qin, J Blackstone… - computers & security, 2018 - Elsevier
Hardware Trojan detection is a very difficult challenge. However, the combination of
symbolic execution and metamorphic testing is useful for detecting hardware Trojans in …
symbolic execution and metamorphic testing is useful for detecting hardware Trojans in …
Dual-purpose mixed-level test generation using swarm intelligence
K Gent, MS Hsiao - 2014 IEEE 23rd Asian Test Symposium, 2014 - ieeexplore.ieee.org
Automatic test pattern generation for non-scan sequential circuits is an extremely
challenging task. If successful, it can offer many benefits to the EDA community, ranging from …
challenging task. If successful, it can offer many benefits to the EDA community, ranging from …
Beyond test pattern generation: Coverage analysis
The size and complexity of the very large scale integrated circuits are ever increasing
because of rapid advancements of deep-submicron and nanometer technologies. It has …
because of rapid advancements of deep-submicron and nanometer technologies. It has …
Fast multi-level test generation at the rtl
K Gent, MS Hsiao - … Society Annual Symposium on VLSI (ISVLSI …, 2016 - ieeexplore.ieee.org
Functional, at-speed vectors continue to provide added value to the testing community as
circuit complexity rises. Complex defects may escape traditional scan vectors and thus often …
circuit complexity rises. Complex defects may escape traditional scan vectors and thus often …
Incremental stack-splitting mechanisms for efficient parallel implementation of search-based AI systems
K Villaverde, E Pontelli, H Guo… - … Conference on Parallel …, 2001 - ieeexplore.ieee.org
Incremental stack-copying is a technique which has been successfully used to support
efficient parallel execution of a variety of search-based Al systems-eg, logic-based and …
efficient parallel execution of a variety of search-based Al systems-eg, logic-based and …
On-line testing of digital vlsi circuits at register transfer level using high level decision diagrams
Abstract Nowadays On-Line Testing (OLT) has became one the essential technique to
detect faults in digital VLSI circuits which occur during their normal operation. However, most …
detect faults in digital VLSI circuits which occur during their normal operation. However, most …
Educational opportunities for US students abroad: how to internationalize and diversify your university
LA Gerhardt, JM Cunningham, DJ Mook… - 31st Annual Frontiers …, 2001 - computer.org
Automatic test pattern generation for non-scan sequential circuits is an extremely
challenging task. If successful, it can offer many benefits to the EDA community, ranging from …
challenging task. If successful, it can offer many benefits to the EDA community, ranging from …
Crossing register transfer level for vlsi circuits
This paper presents an efficient automatic test pattern generation paradigm to gain
confidence in the correctness of designs of circuits. The paradigm is based on selection of a …
confidence in the correctness of designs of circuits. The paradigm is based on selection of a …
A framework for fast test generation at the RTL
K Gent, A Agrawal, MS Hsiao - 2017 IEEE 35th VLSI Test …, 2017 - ieeexplore.ieee.org
We present a framework for high quality functional test generation at the RTL. The method
utilizes static learning to derive cross cycle relationships which helps the search algorithm …
utilizes static learning to derive cross cycle relationships which helps the search algorithm …
A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates
T Strauch - arXiv preprint arXiv:1612.05166, 2016 - arxiv.org
This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL
ATPG model based on" Gate Inherent Faults"(GIF). These GIF are extracted from each …
ATPG model based on" Gate Inherent Faults"(GIF). These GIF are extracted from each …