Power-delay-area efficient design and implementation of Vedic multiplier using 14 nm finfet technology

S Shetkar, M Waje - ICCCE 2021: Proceedings of the 4th International …, 2022 - Springer
Digital Multiplier is the important part of ALU and many other arithmetic operations. VLSI
designers show keen interest in optimizing area, power and delay in multiplier. In this paper …

Design and Analysis of 4* 4-Bit Vedic Multiplier with 32nm CNFET Technology

R Gupta, R Ghughtyal, SP Mahapatra… - 2023 8th International …, 2023 - ieeexplore.ieee.org
Carbon Nanotubes Field Effect Transistors (CNFETs) have shown numerous advantages
over conventional Metal Oxide Semiconductor FETs (MOSFETs) and CMOS in terms of …

Design of high performance 8 bit binary multiplier using vedic multiplication algorithm with 16 nm technology

K Dey, S Chattopadhyay - 2017 1st International Conference …, 2017 - ieeexplore.ieee.org
Vedic mathematics is a system of ancient Indian mathematics, which has a unique technique
of solutions based on only 16 sutras or formulae. This technique is very useful for performing …

[PDF][PDF] Design and analysis of 8-bit Vedic multiplier in 90nm technology using GDI technique

S Sharma, V Sharda - Int. J. Eng. Technol, 2018 - academia.edu
Vedic mathematics is an old mathematics which is more effective than other mathematic
procedures. Vedic maths is utilized as a part of numerous applications, for example …

Power Efficient and High Speed Multiplier Bbased on Ancient Mathematics: A Review

YGP Kumar, BS Karivappa, BH Patil… - … on Electronics and …, 2020 - ieeexplore.ieee.org
Ancient mathematics is the oldest Indian system of mathematics; it has distinct technologies
of solution based on formulae or sutras. Vedic mathematics sutra is very useful for numerous …

[PDF][PDF] Low Power Multiplication through the Urdhva Tiryagbhyam Vedic Algorithm Low Power Digital Systems

Z Fravel - 2017 - zackfravel.github.io
This paper proposes a possible solution to reducing power consumption on CMOS multiplier
circuits. Specifically, this paper looks into one of sixteen of the ancient sutras in Vedic …

Comparision of Adders for High Speed ALU

ADD Dwiwedi, RK Bairwa, C Soni… - … Journal of VLSI …, 2017 - ecc.journalspub.info
In this paper, logic optimized multiplexer based adders are incorporated in selected existing
adders like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder …