State of the art and future perspectives in advanced CMOS technology
The international technology roadmap of semiconductors (ITRS) is approaching the
historical end point and we observe that the semiconductor industry is driving …
historical end point and we observe that the semiconductor industry is driving …
The challenges of advanced CMOS process from 2D to 3D
HH Radamson, Y Zhang, X He, H Cui, J Li, J Xiang… - Applied Sciences, 2017 - mdpi.com
The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit
bricks in integrated circuits (ICs) have constantly changed during the past five decades. The …
bricks in integrated circuits (ICs) have constantly changed during the past five decades. The …
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
A Veloso, T Huynh-Bao, P Matagne, D Jang… - Solid-State …, 2020 - Elsevier
We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …
Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration
H Mertens, R Ritzenthaler, V Pena… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW)
MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. We …
MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. We …
Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Layout design correlated with self-heating effect in stacked nanosheet transistors
L Cai, W Chen, G Du, X Zhang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
With technology node scaling down to 5 nm, the narrow device geometry confines the
material thermal conductivity and further aggravates the self-heating effect in gate-all-around …
material thermal conductivity and further aggravates the self-heating effect in gate-all-around …
First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs
E Capogreco, L Witters, H Arimura… - … on Electron Devices, 2018 - ieeexplore.ieee.org
This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated
on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow …
on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow …
Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition
L Witters, H Arimura, F Sebaai… - IEEE transactions on …, 2017 - ieeexplore.ieee.org
Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated
on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers …
on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers …
GAAFET versus pragmatic FinFET at the 5nm Si-based CMOS technology node
YC Huang, MH Chiang, SJ Wang… - IEEE Journal of the …, 2017 - ieeexplore.ieee.org
Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs
and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected …
and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected …
On the vertically stacked gate-all-around nanosheet and nanowire transistor scaling beyond the 5 nm technology node
H Wong, K Kakushima - Nanomaterials, 2022 - mdpi.com
This work performs a detailed comparison of the channel width folding effectiveness of the
FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire …
FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire …