Adiabatic threshold inverter quantizer for a 3-bit flash ADC

V Moyal, N Tripathi - 2016 International Conference on …, 2016 - ieeexplore.ieee.org
A novel Threshold Inverter Quantizer (TIQ) is suggested in the work to implement a 3-bit, 1.2
V Flash Analog to Digital Converter (ADC). Two Phase Adiabatic Static CMOS Logic …

4× 4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

N Anuar, Y Takahashi, T Sekine - … on VLSI and System-on-Chip, 2010 - ieeexplore.ieee.org
This paper presents the simulation results of a 4× 4-bit array two phase clocked adiabatic
static CMOS logic (2PASCL) multiplier using 0.18 μm standard CMOS technology. We also …

[PDF][PDF] Design of energy efficient arithmetic circuits using charge recovery adiabatic logic

BD Kumar, M Bharathi - … journal of engineering trends and technology, 2013 - academia.edu
Low power has emerged as a principle theme in today electronic industry. Energy efficiency
is one of the most important features of modern electronic systems designed for high speed …

Adiabatic logic: Energy efficient technique for VLSI applications

AK Maurya, G Kumar - 2011 2nd International Conference on …, 2011 - ieeexplore.ieee.org
This paper proposes an energy efficient technique with two-phase clocked adiabatic logic. A
simulative investigation on the proposed circuit has been carried out in SPICE at 0.18 μm …

Energy efficient adiabatic logic for low power vlsi applications

AK Maurya, G Kumar - 2011 International Conference on …, 2011 - ieeexplore.ieee.org
This paper proposes a Adder circuit based on energy efficient two-phase clocked adiabatic
logic. a simulative investigation on the proposed 1-bit full adder has been implemented with …

[PDF][PDF] Design and implementation of low power 8-bit carry-look ahead adder using static cmos logic and adiabatic logic

A Sajid, A Nafees, S Rahman - IJITCS, 2013 - mecs-press.net
Addition forms the basic structure for many processing operations like counting,
multiplication, filtering etc. Adder circuits that add two binary numbers are of great interest for …

Fundamental logics based on two phase clocked adiabatic static CMOS logic

N Anuar, Y Takahashi, T Sekine - 2009 16th IEEE International …, 2009 - ieeexplore.ieee.org
This paper demonstrates some fundamental logic gates employing two phase clocked
adiabatic static CMOS logic (2PASCL) circuit techniques. We design and simulate NOT …

[PDF][PDF] Comparative analysis of conventional CMOS and energy efficient adiabatic logic circuits

G Singh, R Kumar, MK Sharma - International Journal of emerging …, 2013 - Citeseer
In recent years, low power circuit design has been an important issue in System on Chip
(SoC) and VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS …

VLSI implementation of wave shaping diode based adiabatic logic (WSDAL)

D Kumar, M Kumar - International Journal of Electronics, 2021 - Taylor & Francis
This paper presents a new architecture of energy recycling for low power applications. The
reported design is based on the ultra-low-power diode Based on this concept, adiabatic …

Computing with nonequilibrium ratchets

M Kabir, D Unluer, L Li, AW Ghosh… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
Electronic ratchets transduce local spatial asymmetries into directed currents in the absence
of a global drain bias by rectifying temporal signals that reside far from the thermal …