Hardware implementation of POSITs and their application in FPGAs

A Podobas, S Matsuoka - 2018 IEEE International Parallel and …, 2018 - ieeexplore.ieee.org
The failure of Dennard's scaling, the end of Moore's law and the recent developments
regarding Deep Neural Networks (DNN) are leading computer scientists, practitioners and …

FPGA implementation of an efficient FFT processor for FMCW radar signal processing

J Heo, Y Jung, S Lee, Y Jung - Sensors, 2021 - mdpi.com
This paper presents the design and implementation results of an efficient fast Fourier
transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal …

Exploiting posit arithmetic for deep neural networks in autonomous driving applications

M Cococcioni, E Ruffaldi… - … Conference of Electrical …, 2018 - ieeexplore.ieee.org
This paper discusses the introduction of an integrated Posit Processing Unit (PPU) as an
alternative to Floating-point Processing Unit (FPU) for Deep Neural Networks (DNNs) in …

An 826 MOPS, 210uW/MHz unum ALU in 65 nm

F Glaser, S Mach, A Rahimi… - … on Circuits and …, 2018 - ieeexplore.ieee.org
To overcome the limitations of conventional floating-point number formats, an interval
arithmetic and variable-width storage format called universal number (unum) has been …

Area-latency efficient floating point adder using interleaved alignment and normalization

S Pitchai, S Pitchai - Microprocessors and Microsystems, 2023 - Elsevier
The barrel shifter is an indispensable floating-point (FP) adder circuit. It performs the
alignment on the mantissa of the smallest FP number and also normalizes the added …

High-level. NET software implementations of unum type I and posit with simultaneous FPGA implementation using hastlayer

Z Lehóczky, A Retzler, R Tóth, Á Szabó… - Proceedings of the …, 2018 - dl.acm.org
The unum arithmetic framework has been proposed by Gustafson, DJ to address the short-
comings of the IEEE 754 Standard's floating-point. In this paper, we present our software …

[PDF][PDF] Floating-point architectures for energy-efficient transprecision computing

S Mach - 2021 - research-collection.ethz.ch
An era of exponentially improving computing efficiency is coming to an end as Moore's law
falters and Dennard scaling seems to have broken down. The power-wall obstacle fuels a …

Seamless compiler integration of variable precision floating-point arithmetic

TT Jost, Y Durand, C Fabre, A Cohen… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Floating-Point (FP) units in processors are generally limited to supporting a subset of formats
defined by the IEEE 754 standard. As a result, high-efficiency languages and optimizing …

Hardware implementation of basic arithmetics and elementary functions for unum computing

M Bärthel, J Rust, S Paul - 2018 52nd Asilomar Conference on …, 2018 - ieeexplore.ieee.org
The universal number format (unum) is a recently proposed floating point format that solves
rounding issues with interval arithmetic and provides variable exponent and mantissa …

Variable Precision Capabilities in RISC-V Processors

A Bocco, TT Jost, F de Dinechin, A Cohen, Y Durand… - 2019 - research.google
This work proposes to extend RISC-V with Variable Precision (VP) Floating-Point (FP)
capabilities to accelerate scientific computing applications. It adopts the UNUM type I FP …