All-digital duty-cycle corrector with a wide duty correction range for DRAM applications
CH Jeong, A Abdullah, YJ Min… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is
hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time …
hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time …
A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces
This paper presents a single-ended four-level pulse-amplitude modulation (PAM-4)
transmitter using an unstacked tailless current-mode logic (CML) driver for memory …
transmitter using an unstacked tailless current-mode logic (CML) driver for memory …
A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses
IG Thakkar, S Pasricha - 2015 33rd IEEE International …, 2015 - ieeexplore.ieee.org
This paper presents a high-bandwidth 3D graphics DRAM architecture (3D-SGDRAM) with
reduced access time and energy consumption. A novel 3D bank organization is employed …
reduced access time and energy consumption. A novel 3D bank organization is employed …
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations
To mitigate the “Power Wall” challenges for both mobile devices and data centers,
accelerator-rich architecture with normally-off mode has been intensively studied recently …
accelerator-rich architecture with normally-off mode has been intensively studied recently …
A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links
H Hwang, J Kim - IEICE Electronics Express, 2019 - jstage.jst.go.jp
Abstract This Letter presents a 0.8–3.4 GHz process variation insensitive full-swing duty-
cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full …
cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full …
Design and Optimization of Emerging Interconnection and Memory Subsystems for Future Manycore Architectures
IG Thakkar - 2018 - search.proquest.com
With ever-increasing core count and growing performance demand of modern data-centric
applications (eg, big data and internet-of-things (IoT) applications), energy-efficient and low …
applications (eg, big data and internet-of-things (IoT) applications), energy-efficient and low …
Energy-efficient wireline transceivers
G Shu - 2016 - ideals.illinois.edu
Power-efficient wireline transceivers are highly demanded by many applications in high
performance computation and communication systems. Apart from transferring a wide range …
performance computation and communication systems. Apart from transferring a wide range …
[PDF][PDF] A Novel 3D Graphics DRAM Architecture for High Performance and Low Energy Memory Accesses
G Ishan, S Pasricha - engr.colostate.edu
This paper presents a highYbandwidth 3D graphics DRaM architecY ture (3D-SGDRAM)
with reduced access time and energy consumpY tion. a novel 3D ban organization is …
with reduced access time and energy consumpY tion. a novel 3D ban organization is …