[PDF][PDF] Low power residue number system using lookup table decomposition and finite state machine based post computation

B Morasa, P Nimmagadda - Indonesian Journal of Electrical …, 2022 - academia.edu
In this paper, memory optimization and architectural level modifications are introduced for
realizing the low power residue number system (RNS) with improved flexibility for …

Fast FPGA-based multipliers by constant for digital signal processing systems

O Bureneva, S Mironov - Electronics, 2023 - mdpi.com
Traditionally, the usual multipliers are used to multiply signals by a constant, but
multiplication by a constant can be considered as a special operation requiring the …

[PDF][PDF] Implementation of Low Power Generic 2D FIR Filter Bank Architecture Using Memory-based Multipliers.

VK Odugu, CV Narasimhulu, KS Prasad - J. Mobile Multimedia, 2022 - researchgate.net
In this paper, a generic filter bank architecture for 2D FIR filter is proposed using block
processing, symmetry in the filter coefficients, and memorybased multipliers. The different …

A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers

VK Odugu, CV Narasimhulu, KS Prasad - Integration, 2022 - Elsevier
In this paper, a novel block-based generic filter bank architecture is proposed for various
Two Dimensional (2D) symmetry Finite Impulse Response (FIR) filers. It is implemented to …

[HTML][HTML] Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures

PC Ch, JB Seventline - F1000Research, 2023 - ncbi.nlm.nih.gov
Background: This paper presents an efficient two-dimensional (2-D) finite impulse response
(FIR) filter using block processing for two different symmetries. Architectures for a general …

Area and energy-efficient approximate distributive arithmetic architecture for LMS adaptive FIR filter

CS Vinitha, RK Sharma - 2020 International Conference for …, 2020 - ieeexplore.ieee.org
A novel approximate DA architecture is proposed for adaptive FIR filter. LMS algorithm is
used to update the weights of the filter. In this architecture we combined the CSD number …

FPGA design and implementation of an efficient FIR adaptive filter by adopting CSD based approximate distributed arithmetic architecture

CS Vinitha - International Journal of Mobile …, 2024 - inderscienceonline.com
An effective approximate distributed arithmetic (DA) architecture is proposed for adaptive
finite impulse response (FIR) filters. The approximate DA architecture is combined with …

Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

VS Reddy, AV Juliet, ER Thuraka, VK Odugu - Computers and Electrical …, 2024 - Elsevier
The efficient architectures of Two-Dimensional (2D) Finite Impulse Response (FIR) filters are
proposed for image processing applications. The performance metrics such as power …

[PDF][PDF] A Decoder-look up tables for FPGAs

SF Tyurin, RV Vikhorev - Dekoder-Poisk tablic dlya PLIS]",(in Russian) …, 2021 - ezyaccess.in
ABSTRACT The FPGA (Field-Programmable Gate Array) has recently become the popular
hardware and socalled LUTs (Look up Tables) are the basic of the FPGAs logic. For …

FPGA based realization of a High-Speed 8-Tap FIR Filter for Signal Processing Applications

KS Ashim, P Mathur - 2023 4th IEEE Global Conference for …, 2023 - ieeexplore.ieee.org
Memory-based technology is widely used in various applications of digital signal
processing. Compared to other accumulation structures, memory-based structures offer …