Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor
In this paper, a novel Triple metal double gate germanium on insulator vertical TFET is
proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function …
proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function …
[HTML][HTML] Quantization, gate dielectric and channel length effect in double-gate tunnel field-effect transistor
In this work, we investigate the effects of changing device parameters such as channel
length and gate dielectric of n-type double gate (DG) silicon tunneling field effect transistor …
length and gate dielectric of n-type double gate (DG) silicon tunneling field effect transistor …
Core-shell dual-gate nanowire charge-trap memory for synaptic operations for neuromorphic applications
This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire
transistor as an artificial synaptic device with short/long-term potentiation and long-term …
transistor as an artificial synaptic device with short/long-term potentiation and long-term …
Double-gate junctionless 1T DRAM with physical barriers for retention improvement
MHR Ansari, N Navlakha, JY Lee… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
In this article, a double-gate (DG) junction-less (JL) transistor with physical barriers is
proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this …
proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this …
Performance improvement of 1T DRAM by raised source and drain engineering
MHR Ansari, S Cho - IEEE Transactions on Electron Devices, 2021 - ieeexplore.ieee.org
In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET)
with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) …
with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) …
L-shaped tunnel field-effect transistor-based 1T DRAM with improved read current ratio, retention time, and sense margin
In this article, an L-shaped tunnel field-effect transistor (LTFET)-based one-transistor
dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated …
dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated …
Core-shell dual-gate nanowire memory as a synaptic device for neuromorphic application
In this work, a synaptic device for neuromorphic system is proposed and designed to
emulate the biological behaviors in the novel device structure of core-shell dual-gate …
emulate the biological behaviors in the novel device structure of core-shell dual-gate …
Simulation study of multi-source hetero-junction tfet-based capacitor less 1t dram for low power applications
A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-
source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The …
source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The …
Doping dependent assessment of accumulation mode and junctionless FET for 1T DRAM
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper demonstrates the use of double-gate accumulation mode (AM) and junctionless
(JL) transistors for dynamic memory applications at 85° C. The doping dependent …
(JL) transistors for dynamic memory applications at 85° C. The doping dependent …
1T-DRAM with shell-doped architecture
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …