Wormhole routing techniques for directly connected multicomputer systems
P Mohapatra - ACM Computing Surveys (CSUR), 1998 - dl.acm.org
Wormhole routing has emerged as the most widely used switching technique in massively
parallel computers. We present a detailed survey of various techniques for enhancing the …
parallel computers. We present a detailed survey of various techniques for enhancing the …
[图书][B] Interconnection networks
The performance of most digital systems today is limited by their communication or
interconnection, not by their logic or memory. As designers strive to make more efficient use …
interconnection, not by their logic or memory. As designers strive to make more efficient use …
On direct numerical simulation of turbulent flows
G Alfonsi - 2011 - asmedigitalcollection.asme.org
The direct numerical simulation of turbulence (DNS) has become a method of outmost
importance for the investigation of turbulence physics, and its relevance is constantly …
importance for the investigation of turbulence physics, and its relevance is constantly …
Mcboost: Boosting scalability in malware collection and analysis using statistical classification of executables
In this work, we propose Malware Collection Booster (McBoost), a fast statistical malware
detection tool that is intended to improve the scalability of existing malware collection and …
detection tool that is intended to improve the scalability of existing malware collection and …
System-level buffer allocation for application-specific networks-on-chip router design
In this paper, a novel system-level buffer planning algorithm that can be used to customize
the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic …
the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic …
Application-specific buffer space allocation for networks-on-chip router design
J Hu, R Marculescu - … on Computer Aided Design, 2004. ICCAD …, 2004 - ieeexplore.ieee.org
We present a system-level buffer planning algorithm that can be used to customize the
router design in networks-on-chip (NoCs). More precisely, given the traffic characteristics of …
router design in networks-on-chip (NoCs). More precisely, given the traffic characteristics of …
Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O …
RE Kessler, SM Oberlin, SL Scott - US Patent 5,864,738, 1999 - Google Patents
[57] ABSTRACT A system and method of transferring information between a peripheral
device and an MPP system having an interconnect network and a plurality of processing …
device and an MPP system having an interconnect network and a plurality of processing …
Hybrid hypercube/torus architecture
RS Passint, G Thorson, MB Galles - US Patent 6,230,252, 2001 - Google Patents
A scalable multiprocessor system includes processing element nodes. A scalable
interconnect network includes physical communication links interconnecting the processing …
interconnect network includes physical communication links interconnecting the processing …
Domain isolation through virtual network machines
W Salkewicz - US Patent 6,609,153, 2003 - Google Patents
US6609153B1 - Domain isolation through virtual network machines - Google Patents
US6609153B1 - Domain isolation through virtual network machines - Google Patents Domain …
US6609153B1 - Domain isolation through virtual network machines - Google Patents Domain …
Router table lookup mechanism
RS Passint, MB Galles, G Thorson - US Patent 5,970,232, 1999 - Google Patents
A multiprocessor computer system includes processing element nodes interconnected by
physical communication links in a n-dimensional topology, which includes at least two …
physical communication links in a n-dimensional topology, which includes at least two …