A tutorial on multiplierless design of FIR filters: Algorithms and architectures

L Aksoy, P Flores, J Monteiro - Circuits, Systems, and Signal Processing, 2014 - Springer
Finite impulse response (FIR) filtering is a ubiquitous operation in digital signal processing
systems and is generally implemented in full custom circuits due to high-speed and low …

Design of linear phase FIR filters with high probability of achieving minimum number of adders

D Shi, YJ Yu - IEEE Transactions on Circuits and Systems I …, 2010 - ieeexplore.ieee.org
In this paper, an algorithm is proposed for the design of low complexity linear phase finite
impulse response (FIR) filters with optimum discrete coefficients. The proposed algorithm …

Design of power-efficient configurable booth multiplier

SR Kuang, JP Wang - … Transactions on Circuits and Systems I …, 2009 - ieeexplore.ieee.org
In this paper, a power-efficient 16 times 16 configurable Booth multiplier (CBM) that supports
single 16-b, single 8-b, or twin parallel 8-b multiplication operations is proposed. To …

Search algorithms for the multiple constant multiplications problem: Exact and approximate

L Aksoy, EO Güneş, P Flores - Microprocessors and Microsystems, 2010 - Elsevier
This article addresses the multiplication of one data sample with multiple constants using
addition/subtraction and shift operations, ie, the multiple constant multiplications (MCM) …

Low-cost FIR filter designs based on faithfully rounded truncated multiple constant multiplication/accumulation

SF Hsiao, JHZ Jian, MC Chen - IEEE Transactions on Circuits …, 2013 - ieeexplore.ieee.org
Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully
rounded truncated multipliers. We jointly consider the optimization of bit width and hardware …

A polynomial-based time-varying filter structure for the compensation of frequency-response mismatch errors in time-interleaved ADCs

H Johansson - IEEE Journal of Selected Topics in Signal …, 2009 - ieeexplore.ieee.org
This paper introduces a structure for the compensation of frequency-response mismatch
errors in M-channel time-interleaved analog-to-digital converters (ADCs). It makes use of a …

Toward the multiple constant multiplication at minimal hardware cost

R Garcia, A Volkova - … Transactions on Circuits and Systems I …, 2023 - ieeexplore.ieee.org
Multiple Constant Multiplication (MCM) over integers is a frequent operation arising in
embedded systems that require highly optimized hardware. An efficient way is to replace …

Maximally flat CIC compensation filter: Design and multiplierless implementation

A Fernandez-Vazquez… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
This brief introduces a design and implementation of maximally flat cascaded integrator
comb compensation filters. In particular, we consider second-and fourth-order linear phase …

Optimal constant multiplication using integer linear programming

M Kumm - IEEE Transactions on Circuits and Systems II …, 2018 - ieeexplore.ieee.org
Constant multiplication circuits can be realized multiplierless by using additions,
subtractions, and bit-shifts. The problem of finding a multiplication circuit with minimum …

Closed-form design of CIC compensators based on maximally flat error criterion

G Molnar, M Vucic - IEEE transactions on circuits and systems II …, 2011 - ieeexplore.ieee.org
The simplest decimation filter is the cascaded-integrator-comb (CIC) filter. However, its
magnitude response has a high passband droop, which is not tolerable in many …