Disclosed herein are exemplary embodiments of a so-called “X-press” test response
compactor. Certain embodiments of the disclosed compactor comprise an overdrive section …

US PATENT DOCUMENTS FOREIGN PATENT DOCUMENTS 5,642,362 A 6, 1997 Savir EP
O 549. 949 3, 1998 5,680,543 A 10, 1997 Bhawmik JP 63-286780 11, 1988 5,694.402 A …

The present disclosure describes embodiments of a compactor for compressing test results
in an integrated circuit and methods for using and designing such embodiments. The …

A scan test architecture is implemented. The scan test architecture provides a method of
performing scan test of unbalanced scan chains. The scan test architecture generates a …

Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one
exemplary embodiment, a failure log is received including entries indicative of compressed …

Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520. i)
fed by the decompressor (510), a scan circuit (502,504) coupled to the plurality of scan …

Methods, apparatus, and systems for diagnosing failing scan cells from compressed test
responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a …

In embodiments of the disclosed technology, diagnosis of a circuit is performed using
compactor signatures (a technique referred to herein as “signature-based diagnosis”) …

4,320,509 4,503,537 4.513, 418 4,536,881 4,602.210 4,687.988 4,754,215 4,801,870
5,072,178 5,090,035 5,091,908 5,138,619 5,167,034 5,173,906 5,258,986 5,301,199 …

(57) ABSTRACT A method for determining that failures in semiconductor test are due to a
defect potentially causing a hold time violation in a scan cell in a scan chain, counting the …