Knowledge Transfer Framework for PVT Robustness in Analog Integrated Circuits
Process, voltage, and temperature (PVT) variations in chip fabrication or operation pose a
significant challenge to the robustness of analog integrated circuits. Existing design …
significant challenge to the robustness of analog integrated circuits. Existing design …
Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization
Designing analog integrated circuits (ICs), particularly sensors and reference circuits,
requires a significant amount of human expertise and time, largely due to the requirement of …
requires a significant amount of human expertise and time, largely due to the requirement of …
Robust circuit optimization under PVT variations via weight optimization problem reformulation
J Li, Y Li, Y Zeng - Expert Systems with Applications, 2024 - Elsevier
Robust design in analog integrated circuits (ICs) is intricate due to process variations,
culminating in notable performance uncertainties. Contemporary surrogate-based …
culminating in notable performance uncertainties. Contemporary surrogate-based …
Picowatt Dual-Output Voltage Reference Based on Leakage Current Compensation and Diode-Connected Voltage Divider
Y Huang, Y Luo, Y Zeng - Electronics, 2024 - search.proquest.com
A picowatt CMOS voltage reference with dual outputs is proposed and simulated in this
paper based on a standard 65 nm process. To compensate for the leakage current caused …
paper based on a standard 65 nm process. To compensate for the leakage current caused …
A 0.7-V and 10-nA CMOS-Only Voltage Reference with 1-mA Load Driving Capability Based on Gate-Voltage Compensation Loop
Y Luo, W Huang, Y Huang, Y Li… - 2024 IEEE International …, 2024 - ieeexplore.ieee.org
An ultra-low quiescent current CMOS-only voltage reference with load driving capability has
been proposed and simulated in a standard 0.18 μm CMOS process in this paper. A gate …
been proposed and simulated in a standard 0.18 μm CMOS process in this paper. A gate …
A 1.3 nW, 0.014%/V and Dual-output CMOS Voltage Reference with Self-biased Current Source
Y Luo, J Yang, Y Li, Y Zeng - 2024 IEEE Asia Pacific …, 2024 - ieeexplore.ieee.org
A nano-watt CMOS-only and dual-output voltage reference is presented for ultra-low power
applications. The chip was fabricated in a standard 0.18-μm CMOS process. To reduce area …
applications. The chip was fabricated in a standard 0.18-μm CMOS process. To reduce area …
Circuit Optimization over Multiple Process Corners for Analog Electronic Design Automation
J Li, S Wang, Z Li, T Huang, YS Han… - 2023 28th International …, 2023 - ieeexplore.ieee.org
In electronic design automation (EDA), performance deviations caused by process
variations need to be tackled adequately. In this paper, we present a framework to address …
variations need to be tackled adequately. In this paper, we present a framework to address …