With transistors scaling down, aging effects become increasingly significant in circuit design.
Thus, the aging-aware cell timing model is necessary for evaluating the aging-induced delay …

Although Printed Electronics (PE) cannot compete with silicon-based systems in
conventional evaluation metrics, eg, integration density, area and performance, PE offers …

One of the major barriers that CMOS devices face at nanometer scale is increasing
parameter variation due to manufacturing imperfections. Process variations severely inhibit …

一般情况下电子产品在失效前性能已经发生退化, 而传统的寿命预测方法没有利用退化信息.
以智能脱扣器电源模块为研究对象, 分析MOSFET 开关周期和电路薄弱环节储能电容退化之间 …

As the transistor technology nodes shrink into the nano-scales, timing guardbands caused
by aging effects and process variations continue to increase. Approximate computing can …

We propose SAFE (Switching Activity Factor-based Effective Current Source Model) for
aging-aware static timing analysis (STA), a new technique for estimating the timing …

In this chapter, we discuss hardware–software co-design approaches that enable machine
learning inference on ultra-resource-constrained embedded systems. As our use case, we …

With the large-scale expansion and process shrinking of modern integrated circuits, aging
has become one of the main factors threatening circuit reliability. To evaluate the impact of …