A survey of swarm intelligence techniques in VLSI routing problems

X Chen, G Liu, N Xiong, Y Su, G Chen - IEEE Access, 2020 - ieeexplore.ieee.org
Routing is a complex and critical stage in the physical design of Very Large Scale
Integration (VLSI), minimizing interconnect length and delay to optimize overall chip …

Consumer electronics product manufacturing time reduction and optimization using AI-based PCB and VLSI circuit designing

Y Goh, D Jung, G Hwang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Circuit design plays an essential role in all consumer electronics products. Printed circuit
board (PCB) and very-large-scale integration (VLSI) circuit designing requires optimization …

Enumeration and Identification of Unique 3D Spatial Topologies of Interconnected Engineering Systems Using Spatial Graphs

SRT Peddada, NM Dunfield… - Journal of …, 2023 - asmedigitalcollection.asme.org
Systematic enumeration and identification of unique 3D spatial topologies (STs) of complex
engineering systems (such as automotive cooling systems, electric power trains, satellites …

Performance comparison of PSO and its new variants in the context of VLSI global routing

S Nath, JK Sing, SK Sarkar - Particle Swarm Optimization with …, 2018 - books.google.com
Substantial reduction of gate delay occurred in recent times owing to radical decrement of
transistor size. The interconnect length and delay are accordingly increased owing to the …

Automatic Routing of Printed Circuit Board Traces Using Ant Colony Optimization Algorithm

HT de Azambuja, N Nedjah… - 2024 IEEE Latin …, 2024 - ieeexplore.ieee.org
The advancement of electronics engineering enables the reduction of component size and
the increase in operating frequencies. Consequently, electromagnetic tolerance and …

[PDF][PDF] A new approach to routing optimization for cluster-based wireless sensor networks using swarm intelligence

S Nath, A Seal, A Bhattacharya… - Advances in Industrial …, 2017 - aiem.com.my
Enormous growth rate of Wireless Sensor Networks (WSN) in the recent decade mark out a
high demand for efficient scalable routing and aggregation protocols. WSN primarily …

Minimizing wirelength with bend reduction using gradient descent PSO hybrid in VLSI global routing

S Nath, A Shankar, R Sarkar, S Banerjee… - 2021 Devices for …, 2021 - ieeexplore.ieee.org
Contemporary evolution in assembling billions of transistors in a solitary bite of VLSI chip
and additionally the decrease in the dimension of chip from micrometer to nanometer level …

A Multi-Objective Ant Colony Optimization for Routing in Printed Circuit Boards

HT de Azambuja… - Ibero-Latin …, 2024 - publicacoes.softaliza.com.br
Resumo Automatic routing for Very Large-Scale Integration (VLSI) and Printed Circuit Board
(PCB) design is an important tool to facilitate and optimize the work of engineers. Such a tool …

VLSI routing optimization based on modified constricted PSO with iterative RLC delay model

S Nath, PPG Neogi, JK Sing… - … Conference on Current …, 2018 - ieeexplore.ieee.org
Global interconnect delay is increasingly dominated with the scaling of VLSI fabrication
technology where wire minimization, wire-sizing and buffer insertion techniques have found …

Multiple-Criteria Decision Analysis Using VLSI Global Routing

S Nath, R Majumdar - Predictive Analytics, 2021 - taylorfrancis.com
The very large scale integration (VLSI) chip is an important component of an integrated
circuit, which is a prime block-building component used to figure an electronic gadget. The …