Integrated circuit chips with fine-line metal and over-passivation metal

MS Lin, JY Lee, CK Chou - US Patent 7,969,006, 2011 - Google Patents
US7969006B2 - Integrated circuit chips with fine-line metal and over-passivation metal -
Google Patents US7969006B2 - Integrated circuit chips with fine-line metal and over-passivation …
被引用次数：122 相关文章 所有 4 个版本
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Interconnect structure for integrated circuits

JJ Liaw - US Patent 8,405,216, 2013 - Google Patents
The present invention discloses an interconnect structure for an integrated circuit formed on
a semiconductor substrate. In one embodiment, the first conductive layer is formed above …
被引用次数：131 相关文章 所有 4 个版本

Integrated circuit chips with fine-line metal and over-passivation metal

MS Lin, JY Lee, CK Chou - US Patent 8,021,918, 2011 - Google Patents
US8021918B2 - Integrated circuit chips with fine-line metal and over-passivation metal -
Google Patents US8021918B2 - Integrated circuit chips with fine-line metal and over-passivation …
被引用次数：69 相关文章 所有 4 个版本
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Interconnect structure with redundant electrical connectors and associated systems and methods

A Chandolu - US Patent 9,356,009, 2016 - Google Patents
BACKGROUND Packaged semiconductor dies, including memory chips, microprocessor
chips, and imager chips, typically include a semiconductor die mounted on a Substrate and …
被引用次数：34 相关文章 所有 4 个版本

Integrated circuit chips with fine-line metal and over-passivation metal

MS Lin, JY Lee, CK Chou - US Patent App. 11/864,926, 2008 - Google Patents
US20080079461A1 - Integrated circuit chips with fine-line metal and over-passivation metal
- Google Patents US20080079461A1 - Integrated circuit chips with fine-line metal and over-passivation …
被引用次数：64 相关文章 所有 2 个版本
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Through-substrate vias with improved connections

JC Lin, KF Yang - US Patent 9,293,366, 2016 - Google Patents
A device includes a substrate, and a plurality of dielectric layers over the substrate. A
plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least …
被引用次数：46 相关文章 所有 4 个版本

Integrated circuit chips with fine-line metal and over-passivation metal

MS Lin, JY Lee, CK Chou - US Patent 8,004,083, 2011 - Google Patents
US8004083B2 - Integrated circuit chips with fine-line metal and over-passivation metal -
Google Patents US8004083B2 - Integrated circuit chips with fine-line metal and over-passivation …
被引用次数：56 相关文章 所有 4 个版本
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Building metal pillars in a chip for structure support

H Hichri, XH Liu, VJ McGahay, CE Murray… - US Patent …, 2006 - Google Patents
Stacked via pillars, such as metal via pillars, are provided at different and designated
locations in IC chips to support the chip structure during processing and any related …
被引用次数：40 相关文章 所有 4 个版本

Mechanical integrity of nano-interconnects as brittle-matrix nano-composites

H Zahedmanesh, K Vanstreels, QT Le… - Theoretical and Applied …, 2018 - Elsevier
In this study, the mechanical integrity of advanced multilayer nano-interconnects, as
metal/dielectric nano-composites, was investigated using a combination of analytical …
被引用次数：19 相关文章 所有 2 个版本

Impact of back-end-of-line architecture on chip-package-interaction in advanced interconnects

K Vanstreels, H Zahedmanesh, M Gonzalez - Microelectronics Reliability, 2020 - Elsevier
Chip–package interaction (CPI) has become an increasingly important reliability issue in the
microelectronics industry. In order to survive the thermally induced stresses during …
被引用次数：8 相关文章 所有 3 个版本