In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches
In chip design today and for a foreseeable future, the last-level cache and on-chip
interconnect is not only performance critical but also a substantial power consumer. This …
interconnect is not only performance critical but also a substantial power consumer. This …
Agile: A learning-enabled power and performance-efficient network-on-chip design
A number of techniques to achieve power-efficient Network-on-Chips (NoCs) have been
proposed, two of which are power-gating and dynamic voltage and frequency scaling …
proposed, two of which are power-gating and dynamic voltage and frequency scaling …
Energy-efficient time-division multiplexed hybrid-switched noc for heterogeneous multicore systems
NoCs are an integral part of modern multicore processors, they must continuously support
high-throughput low-latency on-chip data communication under a stringent energy budget …
high-throughput low-latency on-chip data communication under a stringent energy budget …
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
DC Juan, D Marculescu - Proceedings of the 2012 ACM/IEEE …, 2012 - dl.acm.org
Network-on-Chips (NoCs) have emerged as the backbone for the inter-core communication
of a chip-multiprocessor (CMP). This paper evaluates and analyzes the advantages of …
of a chip-multiprocessor (CMP). This paper evaluates and analyzes the advantages of …
Providing cost-effective on-chip network bandwidth in GPGPUs
Network-on-chip (NoC) bandwidth has a significant impact on overall performance in
throughput-oriented processors such as GPG-PUs. Although it has been commonly …
throughput-oriented processors such as GPG-PUs. Although it has been commonly …
Designing energy-efficient NoC for real-time embedded systems through slack optimization
Hard real-time embedded systems impose a strict latency requirement on interconnection
subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream …
subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream …
Optimizing the NoC slack through voltage and frequency scaling in hard real-time embedded systems
Hard real-time embedded systems impose a strict latency requirement on interconnection
subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream …
subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream …
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems
Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores
must be designed to satisfy the performance requirements of both latency-sensitive CPU …
must be designed to satisfy the performance requirements of both latency-sensitive CPU …
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors
M Ortín-Obón, D Suárez-Gracia… - Microprocessors and …, 2016 - Elsevier
As chip multiprocessors accommodate a growing number of cores, they demand
interconnection networks that simultaneously provide low latency, high bandwidth, and low …
interconnection networks that simultaneously provide low latency, high bandwidth, and low …
A novel technique for flit traversal in network-on-chip router
With booming intricacy in applications, optimizing latency is a key requirement in Network-
on-Chip (NoC). Bypassing the routers in the intermediate path, the Single Cycle Multi-Hop …
on-Chip (NoC). Bypassing the routers in the intermediate path, the Single Cycle Multi-Hop …