Application mapping is one of the most important dimensions in Network-on-Chip (NoC)
research. It maps the cores of the application to the routers of the NoC topology, affecting the …

The reliance on multi/many-core systems to satisfy the high performance requirement of
complex embedded software applications is increasing. This necessitates the need to …

A super-polynomial lower bound is given for the size of circuits of fixed depth computing the
parity function. Introducing the notion of polynomial-size, constant-depth reduction, similar …

Multiprocessor architectures and platforms have been introduced to extend the applicability
of Moore's law. They depend on concurrency and synchronization in both software and …

In this paper, we analyze the impact of network contention on the application mapping for tile-
based network-on-chip (NoC) architectures. Our main theoretical contribution consists of an …

Efficient run-time mapping of tasks onto Multiprocessor System-on-Chip (MPSoC) is very
challenging especially when new tasks of other applications are also required to be …

According to embodiments of the disclosed subject matter, cores in a many-core processor
may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic …

Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of
cores on a single system-on-chip (SoC). The dependency on multi-core systems to …

This paper presents an efficient binomial IP mapping and optimization algorithm (BMAP) to
reduce the hardware cost of on-chip network (OCN) infrastructure. The complexity of BMAP …

In this survey, we address the concept of network in three different contexts representing the
deterministic, probabilistic, and statistical physics-inspired design paradigms. More …