Word line look ahead read for word line to word line short detection

R Paudel, J Sabde, M Kochar, S Magia - US Patent 9,548,129, 2017 - Google Patents
Techniques are provided for operating a memory device which detect word line short
circuits, such as short circuits between adjacent word lines. In an example implementation …

Self-evaluating array of memory

A Buyuktosunoglu, S Venkataramani, R Joshi… - US Patent …, 2020 - Google Patents
A first voltage may be applied to a memory in a neural network. The memory may include
one or more memory cells. A processor may determine that a first memory cell in the memory …

Sense operation in a stacked memory array device

A Goda, Z Liu - US Patent 8,559,231, 2013 - Google Patents
BACKGROUND Flash memory devices have developed into a popular Source of non-
volatile memory for a wide range of electronic applications. Flash memory devices typically …

Data recovery method after word line-to-word line short circuit

Z Zhang, Y Dong - US Patent 9,785,493, 2017 - Google Patents
US9785493B1 - Data recovery method after word line-to-word line short circuit - Google
Patents US9785493B1 - Data recovery method after word line-to-word line short circuit …

Disturb verify for programming memory cells

K Sarpatwari, A Goda - US Patent 8,638,607, 2014 - Google Patents
Apparatuses and methods for disturb verify for programming operations are described.
Programming memory cells can include applying a number of programming pulses to a first …

Methods and systems for dynamically generating installation configuration files for software

J Laska, W Woods, M Zazrivec - US Patent 8,464,247, 2013 - Google Patents
The present invention provides methods and systems for dynamically generating
configuration files used in installing Software distributions and Software installation testing …

Deep solid state device (deep-SSD): a neural network based persistent data storage

RP Kachare, M Sharma - US Patent 11,449,268, 2022 - Google Patents
According to one general aspect, an apparatus may include a host interface circuit
configured to receive a memory access request, wherein the memory access request is …

Disturb verify for programming memory cells

K Sarpatwari, A Goda - US Patent 9,165,658, 2015 - Google Patents
Apparatuses and methods for disturb Verify for programming operations are described.
Programming memory cells can include applying a number of programming pulses to a first …

Self-evaluating array of memory

A Buyuktosunoglu, S Venkataramani, R Joshi… - US Patent …, 2021 - Google Patents
A first voltage may be applied to a memory in a neural network. The memory may include
one or more memory cells. A processor may determine that a first memory cell in the memory …

Memory access rate

MK Benedict, EL Pope, AC Walton - US Patent 11,474,706, 2022 - Google Patents
A technique includes determining, via an analog circuit, where an access rate of a memory
row associated with a memory device exceeds a threshold. In various examples, upon a …