(57) ABSTRACT A method and computer-usable medium including instruc tions for
performing a method for scheduling executable transactions within a multicore processor …

This invention relates to scheduling threads in a multicore processor. Executable
transactions may be scheduled using at least one distribution queue, which lists executable …

6,653,859 B2 11/2003 Sihlbom et al. 6,711,447 B1 3, 2004 Saeed 6,711,691 B1 3, 2004.
Howard et al. 6,804,632 B2 10/2004 Orenstien et al. 7,249,268 B2 7/2007 Bhandarkar …

A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency
by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone …

A method and computer-usable medium including instructions for performing a method of
managing power consumption in a multicore processor comprising a plurality of processor …

Systems-on-chip often use hardware accelerators or coprocessors to provide efficient
implementations of application-specific functions. The emergence of extensible processor …

Platform-based designed SoC includes one or more processors, RTOS, intellectual property
blocks, memories and an interconnection infrastructure. An associated advantage of …

7,249,268 B2 7/2007 Bhandarkar 7,392.414 B2 6/2008 Bailey et al. 7,502,948 B2 3/2009
Rotem et al. 7,526,661 B2 4/2009 Nakajima et al. 7,617.403 B2 11/2009 Capps, Jr. et al …

This paper presents a high-level synthesizer to map a complete program efficiently on a
dynamically reconfigurable processor (DRP). Initially, we introduce our DRP architecture …

This invention relates to scheduling threads in a multicore processor. Executable
transactions may be scheduled using at least one distribution queue, which lists executable …