Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms
MJ Wibbels, B Chauviere… - 2023 28th IEEE …, 2023 - ieeexplore.ieee.org
Many circuit design methodologies employ combinational logic with feedback to realize
logic functions. Obtaining accurate delay values for cyclic timing paths is an impediment to …
logic functions. Obtaining accurate delay values for cyclic timing paths is an impediment to …
Timing Driven Verification and Optimization of Relative Timed Systems
MJ Wibbels - 2023 - search.proquest.com
Relative timed (RT) circuits have shown area, power, and performance benefits over
synchronous circuits in a number of applications. A primary impediment in the widespread …
synchronous circuits in a number of applications. A primary impediment in the widespread …
Timing and Placement Driven Approaches to Improve Power and Performance in Relative Timed Designs
T Sharma - 2019 - search.proquest.com
The relative timed methodology produces up to 1/2 to 1/20th power at the same performance
in asynchronous modules compared to industry best practice. Commercial EDA tools are …
in asynchronous modules compared to industry best practice. Commercial EDA tools are …
Achieving backend robustness for timed asynchronous circuits
W Lee - 2016 - search.proquest.com
ACHIEVING BACKEND ROBUSTNESS FOR TIMED ASYNCHRONOUS CIRCUITS Page 1
ACHIEVING BACKEND ROBUSTNESS FOR TIMED ASYNCHRONOUS CIRCUITS by William …
ACHIEVING BACKEND ROBUSTNESS FOR TIMED ASYNCHRONOUS CIRCUITS by William …