A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V
This paper presents a 4+ 2T SRAM for embedded searching and in-memory-computing
applications. The proposed SRAM cell uses the n-well as the write wordline to perform write …
applications. The proposed SRAM cell uses the n-well as the write wordline to perform write …
A wide-range level shifter using a modified Wilson current mirror hybrid buffer
SC Luo, CJ Huang, YH Chu - IEEE Transactions on Circuits and …, 2014 - ieeexplore.ieee.org
Wide-range level shifters play critical roles in ultra-low-voltage circuits and systems.
Although state-of-the-art level shifters can convert a subthreshold voltage to the standard …
Although state-of-the-art level shifters can convert a subthreshold voltage to the standard …
Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement
This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline
leakage and a content-addressable-memory-assisted (CAM-assisted) write performance …
leakage and a content-addressable-memory-assisted (CAM-assisted) write performance …
A reliable 8T SRAM for high-speed searching and logic-in-memory operations
To efficiently implement searching and logic functions with the SRAM-based in-memory
computing (IMC), we need to perform computations on bitlines (BLs)(called compute access) …
computing (IMC), we need to perform computations on bitlines (BLs)(called compute access) …
10T SRAM Using Half- Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
N Maroof, BS Kong - IEEE transactions on very large scale …, 2016 - ieeexplore.ieee.org
We present, in this paper, a new 10T static random access memory cell having single ended
decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage …
decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage …
[图书][B] Gain-cell Embedded DRAMs for Low-power VLSI Systems-on-chip
Gain-Cell eDRAM (GC-eDRAM) is an interesting, high-density alternative to SRAM and
conventional 1T-1C eDRAM for a large range of VLSI system-onchip (SoC) applications …
conventional 1T-1C eDRAM for a large range of VLSI system-onchip (SoC) applications …
A 290-mV, 3.34-MHz, 6T SRAM with pMOS access transistors and boosted wordline in 65-nm CMOS technology
This paper presents a six-transistor bitcell SRAM with pMOS access transistor. Utilizing
pMOS access transistor results in lower zero-level degradation (ZLD) and, hence, higher …
pMOS access transistor results in lower zero-level degradation (ZLD) and, hence, higher …
Area and energy-efficient complementary dual-modular redundancy dynamic memory for space applications
R Giterman, L Atias, A Teman - IEEE Transactions on Very …, 2016 - ieeexplore.ieee.org
The limited size and power budgets of space-bound systems often contradict the
requirements for reliable circuit operation within high-radiation environments. In this paper …
requirements for reliable circuit operation within high-radiation environments. In this paper …
CoreVA-MPSoC: A many-core architecture with tightly coupled shared and local data memories
MPSoCs with hierarchical communication infrastructures are promising architectures for low
power embedded systems. Multiple CPU clusters are coupled using an Network-on-Chip …
power embedded systems. Multiple CPU clusters are coupled using an Network-on-Chip …
Optimizing SRAM bitcell reliability and energy for IoT applications
This paper compares six different 8T SRAM bitcells targeting different design space
requirements-such as reliability and low power/energy-for Internet of Things (IoT) …
requirements-such as reliability and low power/energy-for Internet of Things (IoT) …