Enabling resource-efficient aiot system with cross-level optimization: A survey

S Liu, B Guo, C Fang, Z Wang, S Luo… - … Surveys & Tutorials, 2023 - ieeexplore.ieee.org
The emerging field of artificial intelligence of things (AIoT, AI+ IoT) is driven by the
widespread use of intelligent infrastructures and the impressive success of deep learning …

Hardware-accelerated platforms and infrastructures for network functions: A survey of enabling technologies and research studies

P Shantharama, AS Thyagaturu, M Reisslein - IEEE Access, 2020 - ieeexplore.ieee.org
In order to facilitate flexible network service virtualization and migration, network functions
(NFs) are increasingly executed by software modules as so-called “softwarized NFs” on …

A scalable processing-in-memory accelerator for parallel graph processing

J Ahn, S Hong, S Yoo, O Mutlu, K Choi - Proceedings of the 42nd Annual …, 2015 - dl.acm.org
The explosion of digital data and the ever-growing need for fast data analysis have made in-
memory big-data processing in computer systems increasingly important. In particular, large …

PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture

J Ahn, S Yoo, O Mutlu, K Choi - ACM SIGARCH Computer Architecture …, 2015 - dl.acm.org
Processing-in-memory (PIM) is rapidly rising as a viable solution for the memory wall crisis,
rebounding from its unsuccessful attempts in 1990s due to practicality concerns, which are …

DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks

GF Oliveira, J Gómez-Luna, L Orosa, S Ghose… - IEEE …, 2021 - ieeexplore.ieee.org
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …

A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6T bit cell enabling logic-in-memory

S Jeloka, NB Akesh, D Sylvester… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit
cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that …

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

A Farmahini-Farahani, JH Ahn… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
Energy consumed for transferring data across the processor memory hierarchy constitutes a
large fraction of total system energy consumption, and this fraction has steadily increased …

Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures

YS Shao, B Reagen, GY Wei, D Brooks - ACM SIGARCH Computer …, 2014 - dl.acm.org
Hardware specialization, in the form of accelerators that provide custom datapath and
control for specific algorithms and applications, promises impressive performance and …

HRL: Efficient and flexible reconfigurable logic for near-data processing

M Gao, C Kozyrakis - 2016 IEEE International Symposium on …, 2016 - ieeexplore.ieee.org
The energy constraints due to the end of Dennard scaling, the popularity of in-memory
analytics, and the advances in 3D integration technology have led to renewed interest in …

GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies

JS Kim, D Senol Cali, H Xin, D Lee, S Ghose, M Alser… - BMC genomics, 2018 - Springer
Background Seed location filtering is critical in DNA read mapping, a process where billions
of DNA fragments (reads) sampled from a donor are mapped onto a reference genome to …