-Band Amplifiers With 6-dB Noise Figure and Milliwatt-Level 170–200-GHz Doublers in 45-nm CMOS
B Cetinoneri, YA Atesal, A Fung… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
This paper presents low-noise-band amplifiers and milliwatt-level 170-200-GHz output
doublers in 45-nm semiconductor-on-insulator (SOI) CMOS technology. The transistors are …
doublers in 45-nm semiconductor-on-insulator (SOI) CMOS technology. The transistors are …
Pole-converging intrastage bandwidth extension technique for wideband amplifiers
To overcome limitations on bandwidth extension in conventional design techniques, a novel
pole-converging technique with transformer feedback for intrastage bandwidth extension is …
pole-converging technique with transformer feedback for intrastage bandwidth extension is …
Design of a D-band CMOS amplifier utilizing coupled slow-wave coplanar waveguides
This paper validates a design and modeling methodology of coupled slow-wave
waveguides (CS-CPW) by presenting a D-band CMOS low-noise amplifier (LNA) that …
waveguides (CS-CPW) by presenting a D-band CMOS low-noise amplifier (LNA) that …
A W-Band Balanced Power Amplifier Using Broadside Coupled Strip-Line Coupler in SiGe BiCMOS 0.13- Technology
Load-variation insensitivity, for impedance matching between power amplifiers (PAs) and
transmitting antennas, contributes to challenging the design of millimeter-wave wireless …
transmitting antennas, contributes to challenging the design of millimeter-wave wireless …
Millimeter-wave wafer-scale silicon BiCMOS power amplifiers using free-space power combining
YA Atesal, B Cetinoneri, M Chang… - IEEE Transactions …, 2011 - ieeexplore.ieee.org
This paper presents the first millimeter-wave wafer-scale power-amplifier array implemented
in a 0.13-μ m BiCMOS technology. The power combining is done in the free-space using …
in a 0.13-μ m BiCMOS technology. The power combining is done in the free-space using …
A 150 GHz Amplifier With 8 dB Gain and 6 dBm in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines
A 150 GHz amplifier in digital 65 nm CMOS process is presented. Matching loss is reduced
and bandwidth extended by simplistic topology: no dc-block capacitor, shunt-only tuning and …
and bandwidth extended by simplistic topology: no dc-block capacitor, shunt-only tuning and …
High-efficiency E-band power amplifiers and transmitter using gate capacitance linearization in a 65-nm CMOS process
This brief presents a new design technique for high-efficiency CMOS millimeter-wave power
amplifiers (PAs) and the implementations of a two-stage moderate-power PA, a three-stage …
amplifiers (PAs) and the implementations of a two-stage moderate-power PA, a three-stage …
77–110 GHz 65-nm CMOS power amplifier design
KL Wu, KT Lai, R Hu, CF Jou, DC Niu… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper details the development of our millimeter-wave wideband power amplifier
design. By treating the power combiner as an impedance transformer which allows different …
design. By treating the power combiner as an impedance transformer which allows different …
-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized -Core and Transmission Line-Based Zero-Degree Power Combining Networks
This article proposes high-gain, high-output-power, and high-power-added efficiency (PAE)
power amplifiers (PAs) by adopting an output power maximized (OPM) maximum achievable …
power amplifiers (PAs) by adopting an output power maximized (OPM) maximum achievable …
A -Band CMOS Amplifier With a New Dual-Frequency Interstage Matching Technique
DH Kim, D Kim, JS Rieh - IEEE Transactions on Microwave …, 2017 - ieeexplore.ieee.org
A new interstage matching technique has been proposed and successfully applied to a D-
band amplifier in a 65-nm CMOS technology. The proposed technique is based on a …
band amplifier in a 65-nm CMOS technology. The proposed technique is based on a …