This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator.
The advantages of the proposed circuit are low kickback noise and offset. Moreover, low …

Low-activity signals, such as voice, electrocardiogram (ECG), and ultrasonic signals, in the
Internet-of-Things applications have both posed unique challenges and offered special …

Leakage diodes cause deviations in the thermal drift of ultra-low-power two-transistor (2T)
reference circuits, resulting in either convex or concave output voltages against temperature …

This work proposes a RX front-end structure, which is used for channel equalization of 25
Gb/s high-speed links. This design includes two parts, linear equalizer and decision …

Abstract A 56 Gbps 2-tap 4-level pulse amplitude modulation closed-loop decision feedback
equalizer (DFE) is designed in 28 nm CMOS technology. The first-tap feedback signal …

In this research, a second-order delta-sigma modulator (DSM) with 16-bit resolution is
implemented in VHDL and based on FPGA with a time-interleaved (TI) structure. The …

This paper presents a new quarter-rate 4-level pulse amplitude modulation (PAM-4)
decision-feedback equalizer (DFE) architecture targeting short-reach and the onset of …

Driven by the ongoing challenge of designing high-accuracy digital-to-analog converters
(DACs) at the cost of a relatively small area occupation, optimal combination algorithms …

This paper presents a new successive approximation algorithm that can digitize the second-
order difference of signal samples rather than each sample point individually or plain …

This paper presents the design of a sampling network for an 8-bit, 16 GS/s, 16-channel time-
interleaved analog-to-digital converter (ADC) implemented in a 28 nm CMOS process. The …