A 1.5-3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm
CMOS technology is presented in this paper. The proposed ADDLL uses the modified …

In this brief, a four-phase delay-locked loop (DLL) with low phase error, low power
consumption, and small area is presented for time-to-digital conversion application. A highly …

This brief presents an open-loop duty cycle corrector (DCC) with digital falling edge
modulator. The proposed DCC consists of a loop delay chain for edge alignment and a …

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate
(DDR1)–DDR5 applications is proposed. The proposed architecture combines the …

A new time-to-digital converter (TDC)-based fast-lock all-digital delay-locked loop (DLL) with
a built-in duty-cycle corrector (DCC) is presented. The proposed DLL utilizes a new shared …

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The
proposed DLL adopted a dual delay line structure, each delay line was composed of a …

This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-
combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most …

A low-power low-jitter delay locked loop (DLL) with a first order differential closed-loop duty
cycle corrector (DCC) is presented in this paper. The proposed DCC has a differential …

Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2
GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty …

A novel shared time-to-digital converter (TDC)-based, fast-locking, all-digital delay-locked
loop (DLL) incorporating a duty-cycle corrector (DCC)-embedded delay line is introduced …