Oscillation-based prebond TSV test
Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-
Die test that is often necessary to retain a high compound yield for 3-D stacked integrated …
Die test that is often necessary to retain a high compound yield for 3-D stacked integrated …
Challenges and solutions in emerging memory testing
The research and prototyping of new memory technologies are getting a lot of attention in
order to enable new (computer) architectures and provide new opportunities for today's and …
order to enable new (computer) architectures and provide new opportunities for today's and …
TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test
K Chakrabarty, S Deutsch… - 2012 IEEE International …, 2012 - ieeexplore.ieee.org
3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a
promising solution for overcoming interconnect and power bottlenecks in IC design …
promising solution for overcoming interconnect and power bottlenecks in IC design …
Contactless pre-bond TSV test and diagnosis using ring oscillators and multiple voltage levels
S Deutsch, K Chakrabarty - IEEE Transactions on Computer …, 2014 - ieeexplore.ieee.org
Defects in through-silicon vias (TSVs) due to fabrication steps decrease the yield and
reliability of 3-D stacked integrated circuits, hence these defects need to be screened early …
reliability of 3-D stacked integrated circuits, hence these defects need to be screened early …
Scalable design methodology and online algorithm for TSV-cluster defects recovery in highly reliable 3D-NoC systems
3D-Network-on-Chips exploit the benefits of Network-on-Chips and 3D-Integrated Circuits
allowing them to be considered as one of the most advanced and auspicious …
allowing them to be considered as one of the most advanced and auspicious …
Online fault tolerance technique for TSV-based 3-D-IC
Y Zhao, S Khursheed… - IEEE Transactions on Very …, 2014 - ieeexplore.ieee.org
This brief presents the design, validation, and evaluation of an efficient online fault tolerance
technique for fault detection and recovery in presence of three through-silicon-vias (TSV) …
technique for fault detection and recovery in presence of three through-silicon-vias (TSV) …
On effective and efficient in-field TSV repair for stacked 3D ICs
Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining
traction for industry adoption. However, manufacturing processes for TSVs have been …
traction for industry adoption. However, manufacturing processes for TSVs have been …
Machine learning based effective linear regression model for TSV layer assignment in 3DIC
On the integration of 3D IC design, thermal management issues play a significant role. So, it
is required to implement an effective approaches and solutions for integrating 3DIC. The …
is required to implement an effective approaches and solutions for integrating 3DIC. The …
Parametric delay test of post-bond through-silicon vias in 3-D ICs via variable output thresholding analysis
A parametric delay fault could arise in a through-silicon via (TSV) of a 3-D IC due to a
manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield …
manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield …
Fault-Tolerant 3D-NoC architecture and design: recent advances and challenges
In this paper, we survey recent research work in the design of fault-tolerant three-
dimensional (3D) network-on-chip (NoC), which has drawn lots of research attention from …
dimensional (3D) network-on-chip (NoC), which has drawn lots of research attention from …