Physically unclonable functions using two-level finite state machine

V Vijay, K Chaitanya, CS Pittala… - Journal of VLSI …, 2022 - vlsijournal.com
The usage of physically unclonable functions is for authentications, identification
applications, signature generation, IC metering, and cryptographic key generation …

Speech emotion recognition system with librosa

PA Babu, VS Nagaraju… - 2021 10th IEEE …, 2021 - ieeexplore.ieee.org
In this paper, we propose a system that will analyze the speech signals and gather the
emotion from the same efficient solution based on combinations. This system solely served …

Universal shift register designed at low supply voltages in 20 nm FinFET using multiplexer

RR Vallabhuni, J Sravana, CS Pittala, M Divya… - … Systems: Proceedings of …, 2021 - Springer
Shift registers are utilized in personal computer systems as an element of ability, including
RAM and numerous types of registers. Besides, automatic framework tasks including …

Design of unbalanced ternary logic gates and arithmetic circuits

V Vijay, CS Pittala, KC Koteshwaramma… - Journal of VLSI …, 2022 - vlsijournal.com
The design of ternary Logic gates–Ternary NAND, Ternary NOR and Standard Ternary
Inverter based on the 18nm FinFET technology is proposed. The Ternary logic systems …

Biasing Techniques: Validation of 3 to 8 Decoder Modules Using 18nm FinFET Nodes

CS Pittala, M Lavanya, M Saritha… - 2021 2nd …, 2021 - ieeexplore.ieee.org
In this research paper, we planned a low leakage power and high speed decoder for
memory cluster application and proposed modern four strategies. In this paper, the collation …

Energy Efficient Decoder Circuit Using Source Biasing Technique in CNTFET Technology

CS Pittala, M Lavanya, V Vijay, Y Reddy… - 2021 Devices for …, 2021 - ieeexplore.ieee.org
VLSI technology is essential for chip fabrication, and 3 to 8 decoder circuits are used in
electronic gadgets; consistency of design, small, fast, in this proposed circuit, 3 to 8 decoder …

Adaptive and recursive vedic karatsuba multiplier using non linear carry select adder

M Saritha, K Chaitanya, V Vijay… - Journal of VLSI …, 2022 - vlsijournal.com
Adaptive And Recursive Vedic Karatsuba Multiplier Using Non Linear Carry Select Adder Page 1
Journal of VLSI circuits and systems, , ISSN 2582-1458 22 RESEARCH ARTICLE …

Fake currency recognition system using edge detection

PA Babu, P Sridhar… - … Research in Technology …, 2022 - ieeexplore.ieee.org
In this paper, we propose a system for currency recognition system and the detection of fake
Indian currency banknotes using image processing techniques. It is hard for people to …

Universal shift register designed at low supply voltages in 15 nm CNTFET using multiplexer

RR Vallabhuni, M Saritha, S Chikkapally… - International Conference …, 2021 - Springer
Shift registers are important memory element in sequential circuits and also utilized as a
memory element in computers, including RAM and numerous types of registers. Besides …

8-Bit Carry Look Ahead Adder Using MGDI Technique

PA Babu, VS Nagaraju, RR Vallabhuni - IoT and Analytics for Sensor …, 2022 - Springer
High-performance and low power consumption are major factors that describe the
significance of a design in VLSI. At low and ultra-low power applications, power …