A quick safari through the reconfiguration jungle

P Schaumont, I Verbauwhede, K Keutzer… - Proceedings of the 38th …, 2001 - dl.acm.org
Cost effective systems use specialization to optimize factors such as power consumption,
processing throughput, flexibility or combinations thereof. Reconfigurable systems obtain …

The instruction-set extension problem: A survey

C Galuzzi, K Bertels - ACM Transactions on Reconfigurable Technology …, 2011 - dl.acm.org
The extension of a given instruction-set with specialized instructions has become a common
technique used to speed up the execution of applications. By identifying computationally …

Flexbex: A risc-v with a reconfigurable instruction extension

N Dao, A Attwood, B Healy… - … International conference on …, 2020 - ieeexplore.ieee.org
This paper presents an all open-source framework for adding embedded FPGAs into RISC-
V CPUs. In our approach, an eFPGA is directly coupled with the CPU, and through …

The instruction-set extension problem: A survey

C Galuzzi, K Bertels - International Workshop on Applied Reconfigurable …, 2008 - Springer
Over the last years, we have witnessed the increased use of Application-Specific Instruction-
Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction …

RISPP: Rotating instruction set processing platform

L Bauer, M Shafique, S Kramer, J Henkel - Proceedings of the 44th …, 2007 - dl.acm.org
Adaptation in embedded processing is key in order to address efficiency. The concept of
extensible embedded processors works well if a few a-priori known hot spots exist …

Design space exploration for efficient resource utilization in coarse-grained reconfigurable architecture

Y Kim, RN Mahapatra, K Choi - IEEE transactions on very large …, 2009 - ieeexplore.ieee.org
Coarse-grained reconfigurable architectures (CGRAs) aim to achieve both goals of high
performance and flexibility. In addition, power consumption is significant for the …

A case study in reliability-aware design: A resilient LDPC code decoder

M May, M Alles, N Wehn - Proceedings of the conference on Design …, 2008 - dl.acm.org
Chip reliability becomes a great threat to the design of future microelectronic systems with
the continuation of the progressive downscaling of CMOS technologies. Hence increasing …

Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture

Y Kim, I Park, K Choi, Y Paek - … of the 2006 international symposium on …, 2006 - dl.acm.org
Coarse-grained reconfigurable architecture aims to achieve both performance and flexibility.
However, power consumption is no less important for the reconfigurable architecture to be …

Dynamic context compression for low-power coarse-grained reconfigurable architecture

Y Kim, RN Mahapatra - IEEE transactions on very large scale …, 2009 - ieeexplore.ieee.org
Most of the coarse-grained reconfigurable architectures (CGRAs) are composed of
reconfigurable ALU arrays and configuration cache (or context memory) to achieve high …

[PDF][PDF] i-Core: A run-time adaptive processor for embedded multi-core systems

J Henkel, L Bauer, M Hübner, A Grudnitsky - Proceedings of the …, 2011 - Citeseer
We present the i-Core (Invasive Core), an Application Specific Instruction Set Processor
(ASIP) with a run-time adaptive instruction set. Its adaptivity is controlled by the runtime …