Data-aware process networks
C Alias, A Plesco - Proceedings of the 30th ACM SIGPLAN International …, 2021 - dl.acm.org
With the emergence of reconfigurable FPGA circuits as a credible alternative to GPUs for
HPC acceleration, new compilation paradigms are required to map high-level algorithmic …
HPC acceleration, new compilation paradigms are required to map high-level algorithmic …
Improving communication patterns in polyhedral process networks
C Alias - arXiv preprint arXiv:1801.04821, 2018 - arxiv.org
Embedded system performances are bounded by power consumption. The trend is to
offload greedy computations on hardware accelerators as GPU, Xeon Phi or FPGA. FPGA …
offload greedy computations on hardware accelerators as GPU, Xeon Phi or FPGA. FPGA …
[PDF][PDF] FIFO recovery by depth-partitioning is complete on data-aware process networks
C Alias - 2018 - inria.hal.science
Computing performances are bounded by power consumption. The trend is to offload
greedy computations on hardware accelerators as GPU, Xeon Phi or FPGA. FPGA chips …
greedy computations on hardware accelerators as GPU, Xeon Phi or FPGA. FPGA chips …
[PDF][PDF] CASH: Compilation and Analysis, Software and Hardware December 10, 2018
The advent of parallelism in supercomputers and in more classical end-user computers
increases the need for high-level code optimization and improved compilers. Until 2006, the …
increases the need for high-level code optimization and improved compilers. Until 2006, the …
[PDF][PDF] A Complete Bibliography of ACM Transactions on Architecture and Code Optimization
NHF Beebe - 2024 - netlib.sandia.gov
A Complete Bibliography of ACM Transactions on Architecture and Code Optimization Page
1 A Complete Bibliography of ACM Transactions on Architecture and Code Optimization …
1 A Complete Bibliography of ACM Transactions on Architecture and Code Optimization …