US7821806B2 - Nonvolatile semiconductor memory circuit utilizing a MIS transistor as a
memory cell - Google Patents US7821806B2 - Nonvolatile semiconductor memory circuit …

Embodiments include apparatuses, methods, and systems for a physically unclonable
function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate …

G11C11/41—Digital stores characterised by the use of particular electric or magnetic
storage elements; Storage elements therefor using electric elements using semiconductor …

A nonvolatile semiconductor memory circuit includes a selection line, a first bit line, a second
bit line, a first MIS transistor having a first gate coupled to the selection line, a first drain …

The semiconductor memory device includes an initialization memory cell having a first
inverter circuit including a first transistor and a second transistor, and a second inverter …

Embodiments include apparatuses, methods, and systems for a physically unclonable
function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate …

An asymmetric static random access memory (SRAM) device that includes at least one
SRAM cell is provided. The SRAM cell includes the first inverter and the second inverter. The …

An IC cell designed to assert one of multiple possible output states, each with equal
probability, implemented to assert a pre-determined one of the multiple output states based …

A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit,
and memory units, each of the memory units including a latch having a first node and a …

US7414903B2 - Nonvolatile memory device with test mechanism - Google Patents
US7414903B2 - Nonvolatile memory device with test mechanism - Google Patents Nonvolatile …