A review on emerging negative capacitance field effect transistor for low power electronics

SB Rahi, S Tayal, AK Upadhyay - Microelectronics Journal, 2021 - Elsevier
Power consumption is the major concern for conventional CMOS based integrated circuit
and systems. Since there is a scope of lowering supply voltage with steep-subthreshold …

Study the impact of graphene channel over conventional silicon on DC/analog and RF performance of DG dual-material-gate VTFET

B Choudhuri, B Bhowmick - Microelectronics Journal, 2022 - Elsevier
In this article, using a Silvaco TCAD simulator, the impact of Graphene Channel Double
Gate Dual Gate Material Vertical tunnel FET on the analog and RF application is studied. We …

[HTML][HTML] Quantization, gate dielectric and channel length effect in double-gate tunnel field-effect transistor

K Mondol, M Hasan, AH Siddique, S Islam - Results in Physics, 2022 - Elsevier
In this work, we investigate the effects of changing device parameters such as channel
length and gate dielectric of n-type double gate (DG) silicon tunneling field effect transistor …

[PDF][PDF] Optimization of double-gate dual material GeOI-vertical TFET for VLSI circuit design

T Chawla, M Khosla, B Raj - IEEE VLSI Circuits and systems Letter, 2020 - researchgate.net
In this article, Double gate Dual material Germanium on insulator Vertical tunnel field effect
transistor (DGDM-GeOI VTFET) device is proposed for Ultra-low power and high …

Design and analysis of electrostatic doped tunnel CNTFET for various process parameters variation

S Bala, M Khosla - Superlattices and Microstructures, 2018 - Elsevier
In this paper, electrostatic doped Tunnel carbon nano tube field effect transistor (ED-Tunnel
CNTFET) is proposed. Additional gates in the source and drain regions draw an appropriate …

Design and investigation of SiGe heterojunction based charge plasma vertical TFET for biosensing application

S Singh, AKS Chauhan, G Joshi, J Singh - Silicon, 2022 - Springer
This paper explores the Vertical tunnel FET with the introduced layer of SiGe within the
channel/source junction using TCAD. As Tunnel FETs smothered the 60 mV/decade …

An improved analytical modeling and simulation of gate stacked linearly graded work function vertical TFET

S Singh, S Yadav, SK Bhalla - Silicon, 2022 - Springer
In this paper, a 2D analytical potential model for n+ SiGe Gate stacked linearly graded work
function Vertical TFET (n+ SiGe GS-LGW-VTFET) is developed with incorporating the effect …

Design and performance analysis of delta-doped hetro-dielectric geoi vertical tfet

M Mittal, M Khosla, T Chawla - Silicon, 2022 - Springer
This paper illustrates delta-doped Hetro-dielectric Germanium on insulator vertical tunnel
field-effect transistor (DDH-GeOI VTFET) and its 2D simulations are investigated using …

[HTML][HTML] Design and analysis of novel La: HfO2 gate stacked ferroelectric tunnel FET for non-volatile memory applications

N Paras, SB Rahi, AK Upadhyay, M Bharti… - … , Devices, Circuits and …, 2024 - Elsevier
Recent experimental studies have shown lanthanum-doped hafnium oxide (La: HfO 2)
possessing ferroelectric properties. This material is of special interest since it is based on …

Label free detection of biomolecules using SiGe sourced dual electrode doping-less dielectrically modulated tunnel FET

A Singh, SI Amin, S Anand - Silicon, 2020 - Springer
In this work, the performance of a Si 0.5 Ge 0.5 sourced dual electrode doping-less Tunnel
FET (DEDLTFET) biosensor using dielectric modulation is studied for different cavity length …