Regional climate modeling using convection‐permitting models (CPMs; horizontal grid
spacing< 4 km) emerges as a promising framework to provide more reliable climate …

Memory isolation is a key property of a reliable and secure computing system--an access to
one memory address should not have unintended side effects on data stored in other …

Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …

In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be
delayed by other tasks running simultaneously on other cores due to interference in the …

In a multi-core system, interference at shared resources (such as caches and main memory)
slows down applications running on different cores. Accurately estimating the slowdown of …

The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

In this paper, we show that cache partitioning does not necessarily ensure predictable cache
performance in modern COTS multicore platforms that use non-blocking caches to exploit …

This paper describes a novel functional Built-in-Self-Test (BIST) method for microprocessors.
This technique is based on the fundamental principle that complex chips have embedded …

Modern SoCs integrate multiple CPU cores and hardware accelerators (HWAs) that share
the same main memory system, causing interference among memory requests from different …

The emerging hybrid DRAM-NVM architecture is challenging the existing memory
management mechanism at the level of the architecture and operating system. In this paper …