Deep learning neural network classifier using non-volatile memory array
An artificial neural network device that utilizes one or more non-volatile memory arrays as
the synapses. The synapses are configured to receive inputs and to generate therefrom …
the synapses. The synapses are configured to receive inputs and to generate therefrom …
Neural network classifier using array of two-gate non-volatile memory cells
A neural network device having a first plurality of synapses that includes a plurality of
memory cells. Each memory cell includes a floating gate over a first portion of a channel …
memory cells. Each memory cell includes a floating gate over a first portion of a channel …
Decoding system and physical layout for analog neural memory in deep learning artificial neural network
H Van Tran, T Vu, S Hong, S Trinh, A Ly… - US Patent …, 2022 - Google Patents
Various embodiments of word line decoders, control gate decoders, bit line decoders, low
voltage row decoders, and high voltage row decoders and various types of physical layout …
voltage row decoders, and high voltage row decoders and various types of physical layout …
Neural network classifier using array of four-gate non-volatile memory cells
A neural network device with synapses having memory cells each having a floating gate and
a first gate over first and second portions of a channel region, and second and third gates …
a first gate over first and second portions of a channel region, and second and third gates …
Power management for an analog neural memory in a deep learning artificial neural network
US11409352B2 - Power management for an analog neural memory in a deep learning
artificial neural network - Google Patents US11409352B2 - Power management for an …
artificial neural network - Google Patents US11409352B2 - Power management for an …
Parallel bitline nonvolatile memory employing channel-based processing technology
H Nazarian, R Fastow - US Patent 8,681,558, 2014 - Google Patents
Providing for a new combination of non-volatile memory architecture and memory
processing technology is described herein. By way of example, disclosed is a parallel bitline …
processing technology is described herein. By way of example, disclosed is a parallel bitline …
Channel skewing
TE Swanson, PJ Voit, RM Przybilla - US Patent 8,472,279, 2013 - Google Patents
Methods and systems for channel skewing are described. One or more methods for channel
skewing includes providing a number of groups of data signals to a memory component …
skewing includes providing a number of groups of data signals to a memory component …
Neural network classifier using array of three-gate non-volatile memory cells
H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or
switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier …
switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier …
Neural network classifier using array of three-gate non-volatile memory cells
A neural network device with synapses having memory cells each having a floating gate and
a first gate over first and second portions of a channel region disposed between source and …
a first gate over first and second portions of a channel region disposed between source and …
Neural network classifier using array of stacked gate non-volatile memory cells
(57) ABSTRACT A neural network device with synapses having memory cells each having
source and drain regions in a semiconductor substrate with a channel region extending …
source and drain regions in a semiconductor substrate with a channel region extending …