A reliable low standby power 10T SRAM cell with expanded static noise margins
E Abbasian, F Izadinasab… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability
and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross …
and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross …
A FinFET-based low-power, stable 8T SRAM cell with high yield
E Mani, P Nimmagadda, SJ Basha… - … -International Journal of …, 2024 - Elsevier
Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data
and respond quickly to requests. However, achieving low-power and stable SRAM cells …
and respond quickly to requests. However, achieving low-power and stable SRAM cells …
Security and privacy of blockchain-based single-bit cache memory architecture for IoT systems
This paper provides an overview of blockchain technology's security and privacy features, as
well as an overview of IoT-based cache memory and single-bit six transistor static random …
well as an overview of IoT-based cache memory and single-bit six transistor static random …
Design of dual port 9T SRAM cell with parallel processing and high performance computing
Y Chopra, P Mittal - Physica Scripta, 2024 - iopscience.iop.org
To meet industry requirements of higher transistor count SRAM cells this paper is proposing,
a nine-transistor configuration static random access memory (SRAM) cell which is …
a nine-transistor configuration static random access memory (SRAM) cell which is …
Dual-Port 8T SRAM Cell Design with Shorted Gate FinFET for Leakage Reduction and Improved Stability
C Duari, S Birla - Intelligent Computing Techniques for Smart Energy …, 2022 - Springer
Since the CMOS technology has reached to nanometer regime to meet the increasing
demand of smarter and faster device, CMOS circuits have to face various short channel …
demand of smarter and faster device, CMOS circuits have to face various short channel …
Strategical Survey on Static Random Access Memory: A Bibilometric Study
This paper analyzes bibilometrics of articles on Static Random Access Memory, with read
and write assist techniques during the period from the year 2011 to 2021. Different …
and write assist techniques during the period from the year 2011 to 2021. Different …
Cache memory architecture for the convergence of machine learning, Internet of Things (IoT), and blockchain technologies
This chapter describes the need for cache memory architecture for the convergence of
machine learning (ML), the Internet of Things (IoTs), and blockchain technologies with a …
machine learning (ML), the Internet of Things (IoTs), and blockchain technologies with a …