Efficient fault simulation on many-core processors

MA Kochte, M Schaal, HJ Wunderlich… - Proceedings of the 47th …, 2010 - dl.acm.org
Fault simulation is essential in test generation, design for test and reliability assessment of
integrated circuits. Reliability analysis and the simulation of self-test structures are …

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

A Herkersdorf, H Aliee, M Engel, M Glaß… - Microelectronics …, 2014 - Elsevier
Abstract The Resilience Articulation Point (RAP) model aims at provisioning researchers
and developers with a probabilistic fault abstraction and error propagation framework …

Structural test for graceful degradation of NoC switches

A Dalirsani, S Holst, M Elm… - 2011 Sixteenth IEEE …, 2011 - ieeexplore.ieee.org
Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They
can overcome defective cores, links and switches. As a side effect, yield is increased at the …

Efficient simulation of structural faults for the reliability evaluation at system-level

MA Kochte, CG Zoellin, R Baranowski… - 2010 19th IEEE …, 2010 - ieeexplore.ieee.org
In recent technology nodes, reliability is considered a part of the standard design¿ ow at all
levels of embedded system design. While techniques that use only low-level models at gate …

[PDF][PDF] Cross-layer dependability modeling and abstraction in system on chip

A Herkersdorf, M Engel, M Glaß… - … on Silicon Errors …, 2013 - ls12-www.cs.tu-dortmund.de
The Resilience Articulation Point (RAP) model aims at provisioning researchers and
developers with a probabilistic fault abstraction and error propagation framework covering …

Connecting different worlds—Technology abstraction for reliability-aware design and Test

U Schlichtmann, VB Kleeberger… - … , Automation & Test …, 2014 - ieeexplore.ieee.org
The rapid shrinking of device geometries in the nanometer regime requires new technology-
aware design methodologies. These must be able to evaluate the resilience of the circuit …

Machine Learning Support for Logic Diagnosis and Defect Classification

HJ Wunderlich - Machine Learning Support for Fault Diagnosis of …, 2022 - Springer
Innovative manufacturing processes allow the integration of billions of transistors into a
single chip, and the implementation of extremely dense designs, but they also come with …

Efficient multi-level fault simulation of HW/SW systems for structural faults

R Baranowski, S Di Carlo, N Hatami, ME Imhof… - Science China …, 2011 - Springer
In recent technology nodes, reliability is increasingly considered a part of the standard
design flow to be taken into account at all levels of embedded systems design. While …

Multi-layer test and diagnosis for dependable nocs

HJ Wunderlich, M Radetzki - … of the 9th International Symposium on …, 2015 - dl.acm.org
Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both,
connectivity and amount of resources, provide some useful redundancy. These properties …

On covering structural defects in NoCs by functional tests

A Dalirsani, N Hatami, ME Imhof… - 2014 IEEE 23rd …, 2014 - ieeexplore.ieee.org
Structural tests provide high defect coverage by considering the low-level circuit details.
Functional test provides a faster test with reduced test patterns and does not imply additional …